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文件名称:cpu_design

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2014-07-13
  • 文件大小：
    2.32mb
  • 已下载：
    4次
  • 提 供 者：
    l****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu_design/top.lso
cpu_design/top.ngr
cpu_design/top.ngc
cpu_design/cpu_design.xise
cpu_design/top.prj
cpu_design/xst/work/work.sdbl
cpu_design/xst/work/work.sdbx
cpu_design/top.xst
cpu_design/top_xst.xrpt
cpu_design/top.syr
cpu_design/xilinxsim.ini
cpu_design/isim/pn_info
cpu_design/isim/isim_usage_statistics.html
cpu_design/isim/temp/regfile.sdb
cpu_design/isim/temp/glbl.sdb
cpu_design/isim/temp/alu.sdb
cpu_design/isim/temp/line_wb.sdb
cpu_design/isim/temp/line_mem.sdb
cpu_design/isim/temp/line_if.sdb
cpu_design/isim/temp/line_id.sdb
cpu_design/isim/temp/line_ex.sdb
cpu_design/isim/temp/datapath.sdb
cpu_design/isim/temp/controller.sdb
cpu_design/isim/temp/mips.sdb
cpu_design/isim/temp/top.sdb
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000003837283028_1621107508.c
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000003837283028_1621107508.didat
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
cpu_design/isim/regfile_isim_beh.exe.sim/work/regfile_isim_beh.exe_main.c
cpu_design/isim/regfile_isim_beh.exe.sim/work/regfile_isim_beh.exe_main.nt.obj
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000003837283028_1621107508.nt.obj
cpu_design/isim/regfile_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt.obj
cpu_design/isim/regfile_isim_beh.exe.sim/regfile_isim_beh.exe
cpu_design/isim/regfile_isim_beh.exe.sim/isimkernel.log
cpu_design/isim/regfile_isim_beh.exe.sim/netId.dat
cpu_design/isim/regfile_isim_beh.exe.sim/isimcrash.log
cpu_design/isim/regfile_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
cpu_design/isim/regfile_isim_beh.exe.sim/tmp_save/_1
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000003168404140_2725559894.c
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000003168404140_2725559894.didat
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
cpu_design/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.c
cpu_design/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.nt.obj
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt.obj
cpu_design/isim/alu_isim_beh.exe.sim/work/m_00000000003168404140_2725559894.nt.obj
cpu_design/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe
cpu_design/isim/alu_isim_beh.exe.sim/isimkernel.log
cpu_design/isim/alu_isim_beh.exe.sim/netId.dat
cpu_design/isim/alu_isim_beh.exe.sim/isimcrash.log
cpu_design/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
cpu_design/isim/alu_isim_beh.exe.sim/tmp_save/_1
cpu_design/isim/work/regfile.sdb
cpu_design/isim/work/alu.sdb
cpu_design/isim/work/line_wb.sdb
cpu_design/isim/work/line_mem.sdb
cpu_design/isim/work/line_if.sdb
cpu_design/isim/work/line_id.sdb
cpu_design/isim/work/line_ex.sdb
cpu_design/isim/work/datapath.sdb
cpu_design/isim/work/controller.sdb
cpu_design/isim/work/mips.sdb
cpu_design/isim/work/top.sdb
cpu_design/isim/work/glbl.sdb
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000242201878_3092946469.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000242201878_3092946469.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002976548636_4223595934.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002976548636_4223595934.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003837283028_1621107508.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003837283028_1621107508.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000585927973_0363893938.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000585927973_0363893938.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003168404140_2725559894.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003168404140_2725559894.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002467979109_2902755313.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002467979109_2902755313.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002253668453_3511416032.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002253668453_3511416032.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000838974060_0680660568.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000838974060_0680660568.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002944438146_3027548060.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000002944438146_3027548060.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000239720630_2186135220.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000239720630_2186135220.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003183111533_3823007873.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000003183111533_3823007873.didat
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
cpu_design/isim/top_isim_beh.exe.sim/work/top_isim_beh.exe_main.c
cpu_design/isim/top_isim_beh.exe.sim/work/m_00000000000838974060_0680660568.nt.obj
cpu_

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