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文件名称:cpu5.10_modelsim

  • 所属分类：
    ARM-PowerPC-ColdFire-MIPS
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-08-16
  • 文件大小：
    2.54mb
  • 已下载：
    0次
  • 提 供 者：
    五***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用verilog编写的8位最简cpu代码，能实现简单的加减运算，存储运算，以及寄存器操作。-Verilog prepared with 8 simple CPU code, to achieve a simple addition and subtraction, memory operations, as well as register operations.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu5.10_modelsim/accum.v
cpu5.10_modelsim/addr_decode.v
cpu5.10_modelsim/adr.v
cpu5.10_modelsim/alu.v
cpu5.10_modelsim/clk_gen.v
cpu5.10_modelsim/clk_gen.v.bak
cpu5.10_modelsim/counter.v
cpu5.10_modelsim/cpu.asm.rpt
cpu5.10_modelsim/cpu.done
cpu5.10_modelsim/cpu.eda.rpt
cpu5.10_modelsim/cpu.fit.rpt
cpu5.10_modelsim/cpu.fit.smsg
cpu5.10_modelsim/cpu.fit.summary
cpu5.10_modelsim/cpu.flow.rpt
cpu5.10_modelsim/cpu.map.rpt
cpu5.10_modelsim/cpu.map.smsg
cpu5.10_modelsim/cpu.map.summary
cpu5.10_modelsim/cpu.pin
cpu5.10_modelsim/cpu.qpf
cpu5.10_modelsim/cpu.qsf
cpu5.10_modelsim/cpu.qws
cpu5.10_modelsim/cpu.sof
cpu5.10_modelsim/cpu.sta.rpt
cpu5.10_modelsim/cpu.sta.summary
cpu5.10_modelsim/cpu.v
cpu5.10_modelsim/cpu.v.bak
cpu5.10_modelsim/cpu.vo
cpu5.10_modelsim/cputop.v
cpu5.10_modelsim/cputop.v.bak
cpu5.10_modelsim/cpu_nativelink_simulation.rpt
cpu5.10_modelsim/datactl.v
cpu5.10_modelsim/db/cpu.(0).cnf.cdb
cpu5.10_modelsim/db/cpu.(0).cnf.hdb
cpu5.10_modelsim/db/cpu.(1).cnf.cdb
cpu5.10_modelsim/db/cpu.(1).cnf.hdb
cpu5.10_modelsim/db/cpu.(2).cnf.cdb
cpu5.10_modelsim/db/cpu.(2).cnf.hdb
cpu5.10_modelsim/db/cpu.(3).cnf.cdb
cpu5.10_modelsim/db/cpu.(3).cnf.hdb
cpu5.10_modelsim/db/cpu.(4).cnf.cdb
cpu5.10_modelsim/db/cpu.(4).cnf.hdb
cpu5.10_modelsim/db/cpu.(5).cnf.cdb
cpu5.10_modelsim/db/cpu.(5).cnf.hdb
cpu5.10_modelsim/db/cpu.(6).cnf.cdb
cpu5.10_modelsim/db/cpu.(6).cnf.hdb
cpu5.10_modelsim/db/cpu.(7).cnf.cdb
cpu5.10_modelsim/db/cpu.(7).cnf.hdb
cpu5.10_modelsim/db/cpu.(8).cnf.cdb
cpu5.10_modelsim/db/cpu.(8).cnf.hdb
cpu5.10_modelsim/db/cpu.(9).cnf.cdb
cpu5.10_modelsim/db/cpu.(9).cnf.hdb
cpu5.10_modelsim/db/cpu.asm.qmsg
cpu5.10_modelsim/db/cpu.asm_labs.ddb
cpu5.10_modelsim/db/cpu.cbx.xml
cpu5.10_modelsim/db/cpu.cmp.bpm
cpu5.10_modelsim/db/cpu.cmp.cdb
cpu5.10_modelsim/db/cpu.cmp.ecobp
cpu5.10_modelsim/db/cpu.cmp.hdb
cpu5.10_modelsim/db/cpu.cmp.kpt
cpu5.10_modelsim/db/cpu.cmp.logdb
cpu5.10_modelsim/db/cpu.cmp.rdb
cpu5.10_modelsim/db/cpu.cmp_merge.kpt
cpu5.10_modelsim/db/cpu.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
cpu5.10_modelsim/db/cpu.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
cpu5.10_modelsim/db/cpu.db_info
cpu5.10_modelsim/db/cpu.eco.cdb
cpu5.10_modelsim/db/cpu.eda.qmsg
cpu5.10_modelsim/db/cpu.fit.qmsg
cpu5.10_modelsim/db/cpu.hier_info
cpu5.10_modelsim/db/cpu.hif
cpu5.10_modelsim/db/cpu.lpc.html
cpu5.10_modelsim/db/cpu.lpc.rdb
cpu5.10_modelsim/db/cpu.lpc.txt
cpu5.10_modelsim/db/cpu.map.bpm
cpu5.10_modelsim/db/cpu.map.cdb
cpu5.10_modelsim/db/cpu.map.ecobp
cpu5.10_modelsim/db/cpu.map.hdb
cpu5.10_modelsim/db/cpu.map.kpt
cpu5.10_modelsim/db/cpu.map.logdb
cpu5.10_modelsim/db/cpu.map.qmsg
cpu5.10_modelsim/db/cpu.map_bb.cdb
cpu5.10_modelsim/db/cpu.map_bb.hdb
cpu5.10_modelsim/db/cpu.map_bb.logdb
cpu5.10_modelsim/db/cpu.pre_map.cdb
cpu5.10_modelsim/db/cpu.pre_map.hdb
cpu5.10_modelsim/db/cpu.rpp.qmsg
cpu5.10_modelsim/db/cpu.rtlv.hdb
cpu5.10_modelsim/db/cpu.rtlv_sg.cdb
cpu5.10_modelsim/db/cpu.rtlv_sg_swap.cdb
cpu5.10_modelsim/db/cpu.sgate.rvd
cpu5.10_modelsim/db/cpu.sgate_sm.rvd
cpu5.10_modelsim/db/cpu.sgdiff.cdb
cpu5.10_modelsim/db/cpu.sgdiff.hdb
cpu5.10_modelsim/db/cpu.sld_design_entry.sci
cpu5.10_modelsim/db/cpu.sld_design_entry_dsc.sci
cpu5.10_modelsim/db/cpu.smp_dump.txt
cpu5.10_modelsim/db/cpu.sta.qmsg
cpu5.10_modelsim/db/cpu.sta.rdb
cpu5.10_modelsim/db/cpu.sta_cmp.8_slow_1200mv_85c.tdb
cpu5.10_modelsim/db/cpu.syn_hier_info
cpu5.10_modelsim/db/cpu.tiscmp.fastest_slow_1200mv_0c.ddb
cpu5.10_modelsim/db/cpu.tiscmp.fastest_slow_1200mv_85c.ddb
cpu5.10_modelsim/db/cpu.tiscmp.fast_1200mv_0c.ddb
cpu5.10_modelsim/db/cpu.tiscmp.slow_1200mv_0c.ddb
cpu5.10_modelsim/db/cpu.tiscmp.slow_1200mv_85c.ddb
cpu5.10_modelsim/db/cpu.tis_db_list.ddb
cpu5.10_modelsim/db/cpu.tmw_info
cpu5.10_modelsim/db/cpu_global_asgn_op.abo
cpu5.10_modelsim/db/prev_cmp_cpu.asm.qmsg
cpu5.10_modelsim/db/prev_cmp_cpu.eda.qmsg
cpu5.10_modelsim/db/prev_cmp_cpu.fit.qmsg
cpu5.10_modelsim/db/prev_cmp_cpu.map.qmsg
cpu5.10_modelsim/db/prev_cmp_cpu.qmsg
cpu5.10_modelsim/db/prev_cmp_cpu.sta.qmsg
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.atm
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.dfp
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.hdbx
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.kpt
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.logdb
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.cmp.rcf
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.map.atm
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.map.dpi
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.map.hdbx
cpu5.10_modelsim/incremental_db/compiled_partitions/cpu.root_partition.map.kpt
cpu5.10_modelsim/incremental_db/README
cpu5.10_modelsim/machine.v
cpu5.10_modelsim/machinectl.v
cpu5.10_modelsim/ram.v
cpu5.10_modelsim/ram.v.bak
cpu5.10_modelsim/register.v
cpu5.10_modelsim/rom.v
cpu5.10_modelsim/rom.v.bak
cpu5.10_modelsim/simulation/modelsim/cpu.sft
cpu5.10_modelsim/simulation/modelsim/cpu.vo
cpu5.10_m

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