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文件名称:20140825

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Matlab] [源码]
  • 上传时间：
    2014-08-28
  • 文件大小：
    5.29mb
  • 已下载：
    0次
  • 提 供 者：
    li***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
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下载文件列表

20140825/coef.coe
20140825/data_tb.txt
20140825/data_tb_sin.m
20140825/modelsim/d_fir_tb.v
20140825/modelsim/d_fir_wave.do
20140825/modelsim/fir_chuan_tb.v
20140825/modelsim/fir_chuan_wave.do
20140825/rtl/d_fir_top.v
20140825/rtl/fir_chuan.v
20140825/top/d_fir/coef.coe
20140825/top/d_fir/data_tb.txt
20140825/top/d_fir/d_fir.gise
20140825/top/d_fir/d_fir.xise
20140825/top/d_fir/d_fir_tb.fdo
20140825/top/d_fir/d_fir_tb.udo
20140825/top/d_fir/d_fir_tb_wave.fdo
20140825/top/d_fir/d_fir_top.bld
20140825/top/d_fir/d_fir_top.cmd_log
20140825/top/d_fir/d_fir_top.lso
20140825/top/d_fir/d_fir_top.ncd
20140825/top/d_fir/d_fir_top.ngc
20140825/top/d_fir/d_fir_top.ngd
20140825/top/d_fir/d_fir_top.ngr
20140825/top/d_fir/d_fir_top.pad
20140825/top/d_fir/d_fir_top.par
20140825/top/d_fir/d_fir_top.pcf
20140825/top/d_fir/d_fir_top.prj
20140825/top/d_fir/d_fir_top.ptwx
20140825/top/d_fir/d_fir_top.stx
20140825/top/d_fir/d_fir_top.syr
20140825/top/d_fir/d_fir_top.twr
20140825/top/d_fir/d_fir_top.twx
20140825/top/d_fir/d_fir_top.unroutes
20140825/top/d_fir/d_fir_top.xpi
20140825/top/d_fir/d_fir_top.xst
20140825/top/d_fir/d_fir_top_envsettings.html
20140825/top/d_fir/d_fir_top_guide.ncd
20140825/top/d_fir/d_fir_top_map.map
20140825/top/d_fir/d_fir_top_map.mrp
20140825/top/d_fir/d_fir_top_map.ncd
20140825/top/d_fir/d_fir_top_map.ngm
20140825/top/d_fir/d_fir_top_map.xrpt
20140825/top/d_fir/d_fir_top_ngdbuild.xrpt
20140825/top/d_fir/d_fir_top_pad.csv
20140825/top/d_fir/d_fir_top_pad.txt
20140825/top/d_fir/d_fir_top_par.xrpt
20140825/top/d_fir/d_fir_top_summary.html
20140825/top/d_fir/d_fir_top_summary.xml
20140825/top/d_fir/d_fir_top_usage.xml
20140825/top/d_fir/d_fir_top_xst.xrpt
20140825/top/d_fir/ipcore_dir/acc/doc/c_accum_v11_0_readme.txt
20140825/top/d_fir/ipcore_dir/acc/doc/c_accum_v11_0_vinfo.html
20140825/top/d_fir/ipcore_dir/acc/doc/ds213_accum.pdf
20140825/top/d_fir/ipcore_dir/acc.asy
20140825/top/d_fir/ipcore_dir/acc.gise
20140825/top/d_fir/ipcore_dir/acc.ncf
20140825/top/d_fir/ipcore_dir/acc.ngc
20140825/top/d_fir/ipcore_dir/acc.sym
20140825/top/d_fir/ipcore_dir/acc.v
20140825/top/d_fir/ipcore_dir/acc.veo
20140825/top/d_fir/ipcore_dir/acc.xco
20140825/top/d_fir/ipcore_dir/acc.xise
20140825/top/d_fir/ipcore_dir/acc_flist.txt
20140825/top/d_fir/ipcore_dir/acc_xmdf.tcl
20140825/top/d_fir/ipcore_dir/blk_mem_gen_ds512.pdf
20140825/top/d_fir/ipcore_dir/blk_mem_gen_v6_3_readme.txt
20140825/top/d_fir/ipcore_dir/coef.coe
20140825/top/d_fir/ipcore_dir/coregen.cgp
20140825/top/d_fir/ipcore_dir/coregen.log
20140825/top/d_fir/ipcore_dir/core_resources.txt
20140825/top/d_fir/ipcore_dir/create_acc.tcl
20140825/top/d_fir/ipcore_dir/create_muti.tcl
20140825/top/d_fir/ipcore_dir/create_ram_data_in.tcl
20140825/top/d_fir/ipcore_dir/create_ROM_COEF.tcl
20140825/top/d_fir/ipcore_dir/edit_ram_data_in.tcl
20140825/top/d_fir/ipcore_dir/gui_latency.txt
20140825/top/d_fir/ipcore_dir/muti/doc/mult_gen_ds255.pdf
20140825/top/d_fir/ipcore_dir/muti/doc/mult_gen_v11_2_readme.txt
20140825/top/d_fir/ipcore_dir/muti/doc/mult_gen_v11_2_vinfo.html
20140825/top/d_fir/ipcore_dir/muti.asy
20140825/top/d_fir/ipcore_dir/muti.gise
20140825/top/d_fir/ipcore_dir/muti.ncf
20140825/top/d_fir/ipcore_dir/muti.ngc
20140825/top/d_fir/ipcore_dir/muti.sym
20140825/top/d_fir/ipcore_dir/muti.v
20140825/top/d_fir/ipcore_dir/muti.veo
20140825/top/d_fir/ipcore_dir/muti.xco
20140825/top/d_fir/ipcore_dir/muti.xise
20140825/top/d_fir/ipcore_dir/muti_flist.txt
20140825/top/d_fir/ipcore_dir/muti_xmdf.tcl
20140825/top/d_fir/ipcore_dir/ram_data_in/example_design/bmg_wrapper.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/example_design/ram_data_in_top.ucf
20140825/top/d_fir/ipcore_dir/ram_data_in/example_design/ram_data_in_top.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/example_design/ram_data_in_top.xdc
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/implement.bat
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/implement.sh
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/planAhead_rdn.bat
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/planAhead_rdn.sh
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/planAhead_rdn.tcl
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/xst.prj
20140825/top/d_fir/ipcore_dir/ram_data_in/implement/xst.scr
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/addr_gen.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/bmg_stim_gen.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/bmg_tb_pkg.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/bmg_tb_synth.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/bmg_tb_top.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/checker.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/data_gen.vhd
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/functional/isim_tcl_cmds.tcl
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/functional/simulate_isim.bat
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/functional/simulate_mti.do
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/functional/simulate_ncsim.sh
20140825/top/d_fir/ipcore_dir/ram_data_in/simulation/functiona

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