Synplify_Pro/
Synplify_Pro/ALU_Syn_2.prd
Synplify_Pro/ALU_Syn_2.prj
Synplify_Pro/ALU_Syn_demo.prd
Synplify_Pro/ALU_Syn_demo.prj
Synplify_Pro/ALU_Syn_demo.sdc
Synplify_Pro/Mix_src.prd
Synplify_Pro/Mix_src_vhdl.prd
Synplify_Pro/Mix_src_vhdl.prj
Synplify_Pro/Mix_src_vlog.prd
Synplify_Pro/Mix_src_vlog.prj
Synplify_Pro/MyWorkspace.prd
Synplify_Pro/MyWorkspace.prj
Synplify_Pro/rev_1/
Synplify_Pro/rev_1/ALU.fse
Synplify_Pro/rev_1/ALU.srd
Synplify_Pro/rev_1/ALU.srm
Synplify_Pro/rev_1/ALU.srr
Synplify_Pro/rev_1/ALU.srs
Synplify_Pro/rev_1/ALU.sxr
Synplify_Pro/rev_1/ALU.tcl
Synplify_Pro/rev_1/ALU.tlg
Synplify_Pro/rev_1/ALU.vqm
Synplify_Pro/rev_1/ALU.xrf
Synplify_Pro/rev_1/ALU_cons.tcl
Synplify_Pro/rev_1/ALU_rm.tcl
Synplify_Pro/rev_1/AutoConstraint_alu.sdc
Synplify_Pro/rev_1/HDL_DEMO.fse
Synplify_Pro/rev_1/HDL_DEMO.srd
Synplify_Pro/rev_1/HDL_DEMO.srm
Synplify_Pro/rev_1/HDL_DEMO.srr
Synplify_Pro/rev_1/HDL_DEMO.srs
Synplify_Pro/rev_1/HDL_DEMO.sxr
Synplify_Pro/rev_1/HDL_DEMO.ta
Synplify_Pro/rev_1/HDL_DEMO.taq
Synplify_Pro/rev_1/HDL_DEMO.tcl
Synplify_Pro/rev_1/HDL_DEMO.tlg
Synplify_Pro/rev_1/HDL_DEMO.vqm
Synplify_Pro/rev_1/HDL_DEMO.xrf
Synplify_Pro/rev_1/HDL_DEMO_cons.tcl
Synplify_Pro/rev_1/HDL_DEMO_rm.tcl
Synplify_Pro/rev_1/HDL_DEMO_ta.srm
Synplify_Pro/rev_1/fsmviewer.fsm
Synplify_Pro/rev_1/syntmp/
Synplify_Pro/rev_1/syntmp/ALU.plg
Synplify_Pro/rev_1/syntmp/HDL_DEMO.plg
Synplify_Pro/rev_2/
Synplify_Pro/rev_2/.recordref
Synplify_Pro/rev_2/AutoConstraint_top.sdc
Synplify_Pro/rev_2/layer0.tlg
Synplify_Pro/rev_2/layer1.tlg
Synplify_Pro/rev_2/layer2.tlg
Synplify_Pro/rev_2/syntmp/
Synplify_Pro/rev_2/syntmp/top.plg
Synplify_Pro/rev_2/top.fse
Synplify_Pro/rev_2/top.srd
Synplify_Pro/rev_2/top.srm
Synplify_Pro/rev_2/top.srr
Synplify_Pro/rev_2/top.srs
Synplify_Pro/rev_2/top.sxr
Synplify_Pro/rev_2/top.tcl
Synplify_Pro/rev_2/top.vqm
Synplify_Pro/rev_2/top.xrf
Synplify_Pro/rev_2/top_cons.tcl
Synplify_Pro/rev_2/top_rm.tcl
Synplify_Pro/rev_3/
Synplify_Pro/rev_3/.recordref
Synplify_Pro/rev_3/layer0.tlg
Synplify_Pro/rev_3/layer1.tlg
Synplify_Pro/rev_3/layer2.tlg
Synplify_Pro/rev_3/syntmp/
Synplify_Pro/rev_3/syntmp/mux.plg
Synplify_Pro/rev_3/syntmp/rotate.plg
Synplify_Pro/rev_3/syntmp/top.plg
Synplify_Pro/rev_3/syntmp/top1.plg
Synplify_Pro/rev_3/top1.fse
Synplify_Pro/rev_3/top1.srd
Synplify_Pro/rev_3/top1.srm
Synplify_Pro/rev_3/top1.srr
Synplify_Pro/rev_3/top1.srs
Synplify_Pro/rev_3/top1.sxr
Synplify_Pro/rev_3/top1.tcl
Synplify_Pro/rev_3/top1.vqm
Synplify_Pro/rev_3/top1.xrf
Synplify_Pro/rev_3/top1_cons.tcl
Synplify_Pro/rev_3/top1_rm.tcl
Synplify_Pro/source/
Synplify_Pro/source/VHDL/
Synplify_Pro/source/VHDL/ALU.VHD
Synplify_Pro/source/VHDL/HDL_DEMO.VHD
Synplify_Pro/source/mixed/
Synplify_Pro/source/mixed/verilog/
Synplify_Pro/source/mixed/verilog/mux.vhd
Synplify_Pro/source/mixed/verilog/mux21.v
Synplify_Pro/source/mixed/verilog/reg8.vhd
Synplify_Pro/source/mixed/verilog/rotate.vhd
Synplify_Pro/source/mixed/verilog/top.v
Synplify_Pro/source/mixed/vhdl/
Synplify_Pro/source/mixed/vhdl/mux.v
Synplify_Pro/source/mixed/vhdl/mux21.vhd
Synplify_Pro/source/mixed/vhdl/reg8.v
Synplify_Pro/source/mixed/vhdl/rotate.v
Synplify_Pro/source/mixed/vhdl/top.vhd
Synplify_Pro/source/verilog/
Synplify_Pro/source/verilog/ALU.V
Synplify_Pro/source/verilog/HDL_DEMO.V
source/
source/VHDL/
source/VHDL/ALU.VHD
source/VHDL/HDL_DEMO.VHD
source/mixed/
source/mixed/verilog/
source/mixed/verilog/mux.vhd
source/mixed/verilog/mux21.v
source/mixed/verilog/reg8.vhd
source/mixed/verilog/rotate.vhd
source/mixed/verilog/top.v
source/mixed/vhdl/
source/mixed/vhdl/mux.v
source/mixed/vhdl/mux21.vhd
source/mixed/vhdl/reg8.v
source/mixed/vhdl/rotate.v
source/mixed/vhdl/top.vhd
source/verilog/
source/verilog/ALU.V
source/verilog/HDL_DEMO.V
示例说明.doc