db/
db/logic_util_heursitic.dat
db/prev_cmp_UART.qmsg
db/UART.db_info
db/UART.eco.cdb
db/UART.sld_design_entry.sci
incremental_db/
incremental_db/compiled_partitions/
incremental_db/compiled_partitions/UART.root_partition.map.kpt
incremental_db/README
my_uart.v
my_uart.v.bak
output_files/
output_files/UART.asm.rpt
output_files/UART.done
output_files/UART.eda.rpt
output_files/UART.fit.rpt
output_files/UART.fit.smsg
output_files/UART.fit.summary
output_files/UART.flow.rpt
output_files/UART.jdi
output_files/UART.map.rpt
output_files/UART.map.summary
output_files/UART.pin
output_files/UART.pof
output_files/UART.sta.rpt
output_files/UART.sta.summary
simulation/
simulation/modelsim/
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/my_uart.vt
simulation/modelsim/my_uart.vt.bak
simulation/modelsim/rtl_work/
simulation/modelsim/rtl_work/my_uart/
simulation/modelsim/rtl_work/my_uart/verilog.prw
simulation/modelsim/rtl_work/my_uart/verilog.psm
simulation/modelsim/rtl_work/my_uart/_primary.dat
simulation/modelsim/rtl_work/my_uart/_primary.dbs
simulation/modelsim/rtl_work/my_uart/_primary.vhd
simulation/modelsim/rtl_work/my_uart_vlg_tst/
simulation/modelsim/rtl_work/my_uart_vlg_tst/verilog.prw
simulation/modelsim/rtl_work/my_uart_vlg_tst/verilog.psm
simulation/modelsim/rtl_work/my_uart_vlg_tst/_primary.dat
simulation/modelsim/rtl_work/my_uart_vlg_tst/_primary.dbs
simulation/modelsim/rtl_work/my_uart_vlg_tst/_primary.vhd
simulation/modelsim/rtl_work/speed_select/
simulation/modelsim/rtl_work/speed_select/verilog.prw
simulation/modelsim/rtl_work/speed_select/verilog.psm
simulation/modelsim/rtl_work/speed_select/_primary.dat
simulation/modelsim/rtl_work/speed_select/_primary.dbs
simulation/modelsim/rtl_work/speed_select/_primary.vhd
simulation/modelsim/rtl_work/uart_rx/
simulation/modelsim/rtl_work/uart_rx/verilog.prw
simulation/modelsim/rtl_work/uart_rx/verilog.psm
simulation/modelsim/rtl_work/uart_rx/_primary.dat
simulation/modelsim/rtl_work/uart_rx/_primary.dbs
simulation/modelsim/rtl_work/uart_rx/_primary.vhd
simulation/modelsim/rtl_work/uart_tx/
simulation/modelsim/rtl_work/uart_tx/verilog.prw
simulation/modelsim/rtl_work/uart_tx/verilog.psm
simulation/modelsim/rtl_work/uart_tx/_primary.dat
simulation/modelsim/rtl_work/uart_tx/_primary.dbs
simulation/modelsim/rtl_work/uart_tx/_primary.vhd
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_temp/
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/UART.sft
simulation/modelsim/UART.vo
simulation/modelsim/UART_modelsim.xrf
simulation/modelsim/UART_run_msim_rtl_verilog.do
simulation/modelsim/UART_run_msim_rtl_verilog.do.bak
simulation/modelsim/UART_run_msim_rtl_verilog.do.bak1
simulation/modelsim/UART_v.sdo
simulation/modelsim/vsim.wlf
speed_select.v
speed_select.v.bak
UART.out.sdc
UART.qpf
UART.qsf
UART.qws
UART_description.txt
UART_nativelink_simulation.rpt
uart_rx.v
uart_tx.v
uart_tx.v.bak