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文件名称:Crazy_FPGA_Examples

  • 所属分类：
    Special Effects
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-10-22
  • 文件大小：
    9.26mb
  • 已下载：
    0次
  • 提 供 者：
    微***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。-All the supporting source code routines crazy bingo Han Bin will be published book　FPGA design techniques and case development explain　in the video, mainly relates to the development direction of.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Crazy_FPGA_Examples/01_Counter_Design/dev/Counter_Design.qpf
Crazy_FPGA_Examples/01_Counter_Design/dev/Counter_Design.qsf
Crazy_FPGA_Examples/01_Counter_Design/dev/Counter_Design.qws
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.asm.rpt
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.done
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.fit.rpt
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.fit.smsg
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.fit.summary
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.flow.rpt
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.jdi
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.map.rpt
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.map.summary
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.pin
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.sof
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.sta.rpt
Crazy_FPGA_Examples/01_Counter_Design/dev/output_files/Counter_Design.sta.summary
Crazy_FPGA_Examples/01_Counter_Design/dev/VIP_System.sdc
Crazy_FPGA_Examples/01_Counter_Design/dev/VIP_System.sdc.bak
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/Counter_Design.v
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/Counter_Design_TB.cr.mti
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/Counter_Design_TB.mpf
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/Counter_Design_TB.v
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/transcript
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/vsim.wlf
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/vsim_stacktrace.vstf
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/wave.do
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design/verilog.prw
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design/verilog.psm
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design/_primary.dat
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design/_primary.dbs
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design/_primary.vhd
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design_@t@b/verilog.prw
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design_@t@b/verilog.psm
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design_@t@b/_primary.dat
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design_@t@b/_primary.dbs
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/@counter_@design_@t@b/_primary.vhd
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/_info
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/_temp/vlog19ssna
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/_temp/vlog2zrsty
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/_temp/vlogik2gwb
Crazy_FPGA_Examples/01_Counter_Design/sim/Counter_Design_TB/work/_vmake
Crazy_FPGA_Examples/01_Counter_Design/src/Counter_Design.v
Crazy_FPGA_Examples/01_Counter_Design/src/Counter_Design.v.bak
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/LED_Display_Design.qpf
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/LED_Display_Design.qsf
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/LED_Display_Design.qws
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/LED_Display_Design.tcl
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.asm.rpt
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.cdf
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.done
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.fit.rpt
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.fit.smsg
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.fit.summary
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.flow.rpt
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.jdi
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.map.rpt
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.map.smsg
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.map.summary
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.pin
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.pof
Crazy_FPGA_Examples/02-1_LED_Display_Design_8BitAddr/dev/output_files/LED_Display_Design.pti_db_list.ddb
Crazy_FPGA_Examples/02-1_LED_Disp

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