文件名称:uart
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- 上传时间:2014-11-01
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文件大小:684.93kb
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基于Libero11.3平台的带收发FIFO的UART程序-Based Libero11.3 platform with the FIFO UART transceiver program
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.cxf
uart/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
uart/component/work/DESIGN_IO/DESIGN_IO.cxf
uart/component/work/DESIGN_IO/DESIGN_IO.sdb
uart/component/work/uart_rx/testbench.v
uart/component/work/uart_rx/uart_rx.cxf
uart/component/work/uart_rx/uart_rx.sdb
uart/component/work/uart_rx/uart_rx.v
uart/component/work/uart_self/datasheet.xsl
uart/component/work/uart_self/testbench.v
uart/component/work/uart_self/uart_self.cxf
uart/component/work/uart_self/uart_self.sdb
uart/component/work/uart_self/uart_self.v
uart/component/work/uart_self/uart_self_DataSheet.xml
uart/component/work/uart_tx/testbench.v
uart/component/work/uart_tx/uart_tx.cxf
uart/component/work/uart_tx/uart_tx.sdb
uart/component/work/uart_tx/uart_tx.v
uart/designer/impl1/ada03820-1.tmp
uart/designer/impl1/detect.ide_des
uart/designer/impl1/run_designer_tool.log
uart/designer/impl1/run_designer_tool.tcl
uart/designer/impl1/run_pinrpt.tcl
uart/designer/impl1/uart_cs.dat
uart/designer/impl1/uart_self.adb
uart/designer/impl1/uart_self.dat
uart/designer/impl1/uart_self.dtf/verify.log
uart/designer/impl1/uart_self.ide_des
uart/designer/impl1/uart_self.lok
uart/designer/impl1/uart_self.tcl
uart/designer/impl1/uart_self_compile_log.rpt
uart/designer/impl1/uart_self_compile_report.txt
uart/designer/impl1/uart_self_report_pin_byname.txt
uart/designer/impl1/uart_self_report_pin_bynumber.txt
uart/hdl/detect.v
uart/hdl/rx_bps.v
uart/hdl/rx_ctrl.v
uart/hdl/tx_bps.v
uart/hdl/tx_ctrl.v
uart/simulation/modelsim.ini
uart/simulation/modelsim.ini.sav
uart/simulation/presynth/_info
uart/simulation/presynth/_lib.qdb
uart/simulation/presynth/_lib1_10.qdb
uart/simulation/presynth/_lib1_10.qpg
uart/simulation/presynth/_lib1_11.qdb
uart/simulation/presynth/_lib1_11.qpg
uart/simulation/presynth/_vmake
uart/simulation/run.do
uart/simulation/uart_presynth_simulation.log
uart/simulation/vsim.wlf
uart/smartgen/DESIGN_FIRMWARE_work.ixf
uart/smartgen/DESIGN_IO_work.ixf
uart/smartgen/rx_fifo/rx_fifo.cxf
uart/smartgen/rx_fifo/rx_fifo.gen
uart/smartgen/rx_fifo/rx_fifo.log
uart/smartgen/rx_fifo/rx_fifo.v
uart/smartgen/rx_fifo_work.ixf
uart/smartgen/smartgen.aws
uart/smartgen/tx_fifo/tx_fifo.cxf
uart/smartgen/tx_fifo/tx_fifo.gen
uart/smartgen/tx_fifo/tx_fifo.log
uart/smartgen/tx_fifo/tx_fifo.v
uart/smartgen/tx_fifo_work.ixf
uart/smartgen/uart_rx_work.ixf
uart/smartgen/uart_self_work.ixf
uart/smartgen/uart_tx_work.ixf
uart/stimulus/uart.v
uart/stimulus/uart_self.v
uart/synthesis/.recordref_modgen
uart/synthesis/backup/uart_self.srr
uart/synthesis/dm/uart_self_comp.xdm
uart/synthesis/run_options.txt
uart/synthesis/scratchproject.prs
uart/synthesis/synlog/report/uart_self_compiler_notes.txt
uart/synthesis/synlog/report/uart_self_compiler_runstatus.xml
uart/synthesis/synlog/report/uart_self_compiler_warnings.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_area_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_combined_clk.rpt
uart/synthesis/synlog/report/uart_self_fpga_mapper_errors.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_notes.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_opt_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_resourceusage.rpt
uart/synthesis/synlog/report/uart_self_fpga_mapper_runstatus.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_timing_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_warnings.txt
uart/synthesis/synlog/report/uart_self_premap_errors.txt
uart/synthesis/synlog/report/uart_self_premap_notes.txt
uart/synthesis/synlog/report/uart_self_premap_runstatus.xml
uart/synthesis/synlog/report/uart_self_premap_warnings.txt
uart/synthesis/synlog/uart_self_fpga_mapper.srr
uart/synthesis/synlog/uart_self_fpga_mapper.srr_Min
uart/synthesis/synlog/uart_self_fpga_mapper.szr
uart/synthesis/synlog/uart_self_fpga_mapper.xck
uart/synthesis/synlog/uart_self_premap.srr
uart/synthesis/synlog/uart_self_premap.szr
uart/synthesis/synlog.tcl
uart/synthesis/synplify.log
uart/synthesis/syntmp/closed.png
uart/synthesis/syntmp/cmdrec_compiler.log
uart/synthesis/syntmp/cmdrec_fpga_mapper.log
uart/synthesis/syntmp/cmdrec_premap.log
uart/synthesis/syntmp/namekey.txt
uart/synthesis/syntmp/open.png
uart/synthesis/syntmp/run_option.xml
uart/synthesis/syntmp/statusReport.html
uart/synthesis/syntmp/uart_self.plg
uart/synthesis/syntmp/uart_self_srr.htm
uart/synthesis/syntmp/uart_self_toc.htm
uart/synthesis/synwork/.cckTransfer
uart/synthesis/synwork/uart_self_comp.fdep
uart/synthesis/synwork/uart_self_comp.srs
uart/synthesis/synwork/uart_self_comp.tlg
uart/synthesis/synwork/uart_self_prem.fse
uart/synthesis/synwork/uart_self_prem.srd
uart/synthesis/traplog.tlg
uart/synthesis/uart_self.areasrr
uart/synthesis/uart_self.edn
uart/synthesis/uart_self.fse
uart/synthesis/uart_self.htm
uart/synthesis/uart_self.map
uart/synthesis/uart_self.pdc
uart/synthesis/uart_self.sap
uart/synthesis/uart_self.sdf
uart/synthesis/uart_self.so
uart/synthesis/uart_self.srd
uart/synthesis/uart_self.srm
uart/synthesis/uart_self.srr
uart/synthesis/uart_self.srs
uart/synthesis/uart_self_scck.rpt
uart/synt
uart/component/work/DESIGN_FIRMWARE/DESIGN_FIRMWARE.sdb
uart/component/work/DESIGN_IO/DESIGN_IO.cxf
uart/component/work/DESIGN_IO/DESIGN_IO.sdb
uart/component/work/uart_rx/testbench.v
uart/component/work/uart_rx/uart_rx.cxf
uart/component/work/uart_rx/uart_rx.sdb
uart/component/work/uart_rx/uart_rx.v
uart/component/work/uart_self/datasheet.xsl
uart/component/work/uart_self/testbench.v
uart/component/work/uart_self/uart_self.cxf
uart/component/work/uart_self/uart_self.sdb
uart/component/work/uart_self/uart_self.v
uart/component/work/uart_self/uart_self_DataSheet.xml
uart/component/work/uart_tx/testbench.v
uart/component/work/uart_tx/uart_tx.cxf
uart/component/work/uart_tx/uart_tx.sdb
uart/component/work/uart_tx/uart_tx.v
uart/designer/impl1/ada03820-1.tmp
uart/designer/impl1/detect.ide_des
uart/designer/impl1/run_designer_tool.log
uart/designer/impl1/run_designer_tool.tcl
uart/designer/impl1/run_pinrpt.tcl
uart/designer/impl1/uart_cs.dat
uart/designer/impl1/uart_self.adb
uart/designer/impl1/uart_self.dat
uart/designer/impl1/uart_self.dtf/verify.log
uart/designer/impl1/uart_self.ide_des
uart/designer/impl1/uart_self.lok
uart/designer/impl1/uart_self.tcl
uart/designer/impl1/uart_self_compile_log.rpt
uart/designer/impl1/uart_self_compile_report.txt
uart/designer/impl1/uart_self_report_pin_byname.txt
uart/designer/impl1/uart_self_report_pin_bynumber.txt
uart/hdl/detect.v
uart/hdl/rx_bps.v
uart/hdl/rx_ctrl.v
uart/hdl/tx_bps.v
uart/hdl/tx_ctrl.v
uart/simulation/modelsim.ini
uart/simulation/modelsim.ini.sav
uart/simulation/presynth/_info
uart/simulation/presynth/_lib.qdb
uart/simulation/presynth/_lib1_10.qdb
uart/simulation/presynth/_lib1_10.qpg
uart/simulation/presynth/_lib1_11.qdb
uart/simulation/presynth/_lib1_11.qpg
uart/simulation/presynth/_vmake
uart/simulation/run.do
uart/simulation/uart_presynth_simulation.log
uart/simulation/vsim.wlf
uart/smartgen/DESIGN_FIRMWARE_work.ixf
uart/smartgen/DESIGN_IO_work.ixf
uart/smartgen/rx_fifo/rx_fifo.cxf
uart/smartgen/rx_fifo/rx_fifo.gen
uart/smartgen/rx_fifo/rx_fifo.log
uart/smartgen/rx_fifo/rx_fifo.v
uart/smartgen/rx_fifo_work.ixf
uart/smartgen/smartgen.aws
uart/smartgen/tx_fifo/tx_fifo.cxf
uart/smartgen/tx_fifo/tx_fifo.gen
uart/smartgen/tx_fifo/tx_fifo.log
uart/smartgen/tx_fifo/tx_fifo.v
uart/smartgen/tx_fifo_work.ixf
uart/smartgen/uart_rx_work.ixf
uart/smartgen/uart_self_work.ixf
uart/smartgen/uart_tx_work.ixf
uart/stimulus/uart.v
uart/stimulus/uart_self.v
uart/synthesis/.recordref_modgen
uart/synthesis/backup/uart_self.srr
uart/synthesis/dm/uart_self_comp.xdm
uart/synthesis/run_options.txt
uart/synthesis/scratchproject.prs
uart/synthesis/synlog/report/uart_self_compiler_notes.txt
uart/synthesis/synlog/report/uart_self_compiler_runstatus.xml
uart/synthesis/synlog/report/uart_self_compiler_warnings.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_area_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_combined_clk.rpt
uart/synthesis/synlog/report/uart_self_fpga_mapper_errors.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_notes.txt
uart/synthesis/synlog/report/uart_self_fpga_mapper_opt_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_resourceusage.rpt
uart/synthesis/synlog/report/uart_self_fpga_mapper_runstatus.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_timing_report.xml
uart/synthesis/synlog/report/uart_self_fpga_mapper_warnings.txt
uart/synthesis/synlog/report/uart_self_premap_errors.txt
uart/synthesis/synlog/report/uart_self_premap_notes.txt
uart/synthesis/synlog/report/uart_self_premap_runstatus.xml
uart/synthesis/synlog/report/uart_self_premap_warnings.txt
uart/synthesis/synlog/uart_self_fpga_mapper.srr
uart/synthesis/synlog/uart_self_fpga_mapper.srr_Min
uart/synthesis/synlog/uart_self_fpga_mapper.szr
uart/synthesis/synlog/uart_self_fpga_mapper.xck
uart/synthesis/synlog/uart_self_premap.srr
uart/synthesis/synlog/uart_self_premap.szr
uart/synthesis/synlog.tcl
uart/synthesis/synplify.log
uart/synthesis/syntmp/closed.png
uart/synthesis/syntmp/cmdrec_compiler.log
uart/synthesis/syntmp/cmdrec_fpga_mapper.log
uart/synthesis/syntmp/cmdrec_premap.log
uart/synthesis/syntmp/namekey.txt
uart/synthesis/syntmp/open.png
uart/synthesis/syntmp/run_option.xml
uart/synthesis/syntmp/statusReport.html
uart/synthesis/syntmp/uart_self.plg
uart/synthesis/syntmp/uart_self_srr.htm
uart/synthesis/syntmp/uart_self_toc.htm
uart/synthesis/synwork/.cckTransfer
uart/synthesis/synwork/uart_self_comp.fdep
uart/synthesis/synwork/uart_self_comp.srs
uart/synthesis/synwork/uart_self_comp.tlg
uart/synthesis/synwork/uart_self_prem.fse
uart/synthesis/synwork/uart_self_prem.srd
uart/synthesis/traplog.tlg
uart/synthesis/uart_self.areasrr
uart/synthesis/uart_self.edn
uart/synthesis/uart_self.fse
uart/synthesis/uart_self.htm
uart/synthesis/uart_self.map
uart/synthesis/uart_self.pdc
uart/synthesis/uart_self.sap
uart/synthesis/uart_self.sdf
uart/synthesis/uart_self.so
uart/synthesis/uart_self.srd
uart/synthesis/uart_self.srm
uart/synthesis/uart_self.srr
uart/synthesis/uart_self.srs
uart/synthesis/uart_self_scck.rpt
uart/synt
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