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文件名称:adder_sub_mul

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  • 上传时间:
    2014-11-18
  • 文件大小:
    384.94kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

加法器,减法器,乘法器,超前进位,一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

adder_sub_mul/adder_1/adder1_v.JPG
adder_sub_mul/adder_1/adder_1.JPG
adder_sub_mul/adder_1/adder_1.v
adder_sub_mul/adder_1/adder_1.v.bak
adder_sub_mul/adder_1/vsim.wlf
adder_sub_mul/adder_1/work/@_opt/vopt9zd3ir
adder_sub_mul/adder_1/work/@_opt/voptasr77g
adder_sub_mul/adder_1/work/@_opt/voptjr6bs8
adder_sub_mul/adder_1/work/@_opt/voptkihfe0
adder_sub_mul/adder_1/work/@_opt/voptmcwj3r
adder_sub_mul/adder_1/work/@_opt/voptybaqmg
adder_sub_mul/adder_1/work/@_opt/voptz5mva8
adder_sub_mul/adder_1/work/@_opt/_deps
adder_sub_mul/adder_1/work/@_opt2/vopt9eftz1
adder_sub_mul/adder_1/work/@_opt2/voptbjfqnj
adder_sub_mul/adder_1/work/@_opt2/voptdrfkd5
adder_sub_mul/adder_1/work/@_opt2/voptfxfh4q
adder_sub_mul/adder_1/work/@_opt2/vopttgz8va
adder_sub_mul/adder_1/work/@_opt2/voptwmz5iw
adder_sub_mul/adder_1/work/@_opt2/voptytz29e
adder_sub_mul/adder_1/work/@_opt2/_deps
adder_sub_mul/adder_1/work/adder_1/_primary.dat
adder_sub_mul/adder_1/work/adder_1/_primary.dbs
adder_sub_mul/adder_1/work/adder_1/_primary.vhd
adder_sub_mul/adder_1/work/_info
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/vopt4s1d7q
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/vopt9e8vs5
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/voptd7a81x
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/voptiwgnjb
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/voptnmi3v2
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/voptvashdh
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/voptz3vyk8
adder_sub_mul/adder_1/work/_temp/voptb0mftm/@_opt1.deleted/_deps
adder_sub_mul/adder_1/work/_vmake
adder_sub_mul/adder_1/[invalid]count4/count4.cr.mti
adder_sub_mul/adder_1/[invalid]count4/count4.mpf
adder_sub_mul/adder_1/[invalid]count4/count4.v
adder_sub_mul/adder_1/[invalid]count4/count_tp.v
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/adder1.cr.mti
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/adder1.JPG
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/adder1.mpf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/adder1.v
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/vsim.wlf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/vopths9hib
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptij0ejq
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptjdqak3
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptk7e7mf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptm154nv
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptnvv0q7
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptqmixqj
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptrf9trz
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/vopts90qsb
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptt3qjtq
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptvxdgv3
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptwq4dwf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptxhv9xv
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptybi6y7
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/voptz593zj
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/@_opt/_deps
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/adder_1/_primary.dat
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/adder_1/_primary.dbs
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/adder_1/_primary.vhd
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/h_adder/_primary.dat
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/h_adder/_primary.dbs
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/h_adder/_primary.vhd
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/or2a/_primary.dat
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/or2a/_primary.dbs
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/or2a/_primary.vhd
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/_info
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder1/work/_vmake
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/adder4.JPG
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/adder4.v
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/vsim.wlf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptszdnt3
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/vopttzbwny
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptvz92js
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptwz78fk
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptxz5ebf
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptyz3k7a
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/voptzz1t35
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/@_opt/_deps
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/adder8/_primary.dat
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/adder8/_primary.dbs
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/adder8/_primary.vhd
adder_sub_mul/adder_1/[invalid]count4/sy_1/adder4/work/_info
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