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文件名称:jisuanqi

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    2014-11-29
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    5.32mb
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fpga开发板实现按键两位数加减乘除运算。通过数码管显示-FPGA development board to achieve key two digit add, subtract, multiply and divide operations. Through the digital tube display


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下载文件列表

jisuanqi/jisuanqi.qpf
jisuanqi/jisuanqi.qsf
jisuanqi/anjian.v
jisuanqi/anjian.v.bak
jisuanqi/display.v
jisuanqi/sw.v
jisuanqi/sw.v.bak
jisuanqi/xuanze.v
jisuanqi/display.v.bak
jisuanqi/xuanze.v.bak
jisuanqi/jisuan.v
jisuanqi/jisuan.v.bak
jisuanqi/fa.v
jisuanqi/les.v
jisuanqi/top.v
jisuanqi/top.v.bak
jisuanqi/fa.v.bak
jisuanqi/jisuanqi.v
jisuanqi/jisuanqi.v.bak
jisuanqi/jisuanqi_nativelink_simulation.rpt
jisuanqi/jisuanqi.qws
jisuanqi/simulation/modelsim/jisuanqi_modelsim.xrf
jisuanqi/simulation/modelsim/jisuanqi_8l_1000mv_100c_slow.vo
jisuanqi/simulation/modelsim/jisuanqi_8l_1000mv_-40c_slow.vo
jisuanqi/simulation/modelsim/jisuanqi_min_1000mv_-40c_fast.vo
jisuanqi/simulation/modelsim/jisuanqi.vo
jisuanqi/simulation/modelsim/jisuanqi_8l_1000mv_100c_v_slow.sdo
jisuanqi/simulation/modelsim/jisuanqi_8l_1000mv_-40c_v_slow.sdo
jisuanqi/simulation/modelsim/jisuanqi_min_1000mv_-40c_v_fast.sdo
jisuanqi/simulation/modelsim/jisuanqi_v.sdo
jisuanqi/simulation/modelsim/jisuanqi.vt
jisuanqi/simulation/modelsim/jisuanqi.vt.bak
jisuanqi/simulation/modelsim/jisuanqi_run_msim_rtl_verilog.do
jisuanqi/simulation/modelsim/msim_transcript
jisuanqi/simulation/modelsim/modelsim.ini
jisuanqi/simulation/modelsim/vsim.wlf
jisuanqi/simulation/modelsim/jisuanqi.sft
jisuanqi/simulation/modelsim/rtl_work/_info
jisuanqi/simulation/modelsim/rtl_work/_vmake
jisuanqi/simulation/modelsim/rtl_work/jisuanqi_vlg_tst/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/jisuanqi_vlg_tst/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/jisuanqi_vlg_tst/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/jisuanqi_vlg_tst/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/jisuanqi_vlg_tst/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/jisuanqi/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/jisuanqi/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/jisuanqi/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/jisuanqi/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/jisuanqi/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/led/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/led/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/led/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/led/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/led/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/fa/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/fa/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/fa/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/fa/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/fa/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/yunsuan/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/yunsuan/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/yunsuan/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/yunsuan/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/yunsuan/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/xuanze/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/xuanze/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/xuanze/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/xuanze/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/xuanze/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/sw/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/sw/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/sw/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/sw/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/sw/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/display/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/display/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/display/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/display/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/display/_primary.dat
jisuanqi/simulation/modelsim/rtl_work/anjian/_primary.vhd
jisuanqi/simulation/modelsim/rtl_work/anjian/verilog.psm
jisuanqi/simulation/modelsim/rtl_work/anjian/verilog.prw
jisuanqi/simulation/modelsim/rtl_work/anjian/_primary.dbs
jisuanqi/simulation/modelsim/rtl_work/anjian/_primary.dat
jisuanqi/incremental_db/README
jisuanqi/incremental_db/compiled_partitions/jisuanqi.db_info
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.kpt
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.cmp.logdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.cmp.kpt
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.dpi
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.cdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.hdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.hbdb.hb_info
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.hbdb.cdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.hbdb.hdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.map.hbdb.sig
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.cmp.rcfdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.cmp.cdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_partition.cmp.hdb
jisuanqi/incremental_db/compiled_partitions/jisuanqi.root_p

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