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文件名称:start_lab4

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2014-12-05
  • 文件大小：
    21.16mb
  • 已下载：
    0次
  • 提 供 者：
    林***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数-

Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
(系统自动生成,下载前可以参看下载内容)

下载文件列表

start_lab4/
start_lab4/db/
start_lab4/db/altsyncram_iss3.tdf
start_lab4/db/altsyncram_ups3.tdf
start_lab4/db/cmpr_efc.tdf
start_lab4/db/cmpr_gfc.tdf
start_lab4/db/cmpr_hfc.tdf
start_lab4/db/cntr_0fi.tdf
start_lab4/db/cntr_22j.tdf
start_lab4/db/cntr_5fi.tdf
start_lab4/db/cntr_95j.tdf
start_lab4/db/cntr_ldi.tdf
start_lab4/db/cntr_odi.tdf
start_lab4/db/cntr_p1j.tdf
start_lab4/db/dec_segment.(0).cnf.cdb
start_lab4/db/dec_segment.(0).cnf.hdb
start_lab4/db/dec_segment.asm.qmsg
start_lab4/db/dec_segment.asm.rdb
start_lab4/db/dec_segment.asm_labs.ddb
start_lab4/db/dec_segment.cbx.xml
start_lab4/db/dec_segment.cmp.bpm
start_lab4/db/dec_segment.cmp.cdb
start_lab4/db/dec_segment.cmp.ecobp
start_lab4/db/dec_segment.cmp.hdb
start_lab4/db/dec_segment.cmp.kpt
start_lab4/db/dec_segment.cmp.logdb
start_lab4/db/dec_segment.cmp.rdb
start_lab4/db/dec_segment.cmp_merge.kpt
start_lab4/db/dec_segment.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
start_lab4/db/dec_segment.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
start_lab4/db/dec_segment.db_info
start_lab4/db/dec_segment.eco.cdb
start_lab4/db/dec_segment.fit.qmsg
start_lab4/db/dec_segment.hier_info
start_lab4/db/dec_segment.hif
start_lab4/db/dec_segment.lpc.html
start_lab4/db/dec_segment.lpc.rdb
start_lab4/db/dec_segment.lpc.txt
start_lab4/db/dec_segment.map.bpm
start_lab4/db/dec_segment.map.cdb
start_lab4/db/dec_segment.map.ecobp
start_lab4/db/dec_segment.map.hdb
start_lab4/db/dec_segment.map.kpt
start_lab4/db/dec_segment.map.logdb
start_lab4/db/dec_segment.map.qmsg
start_lab4/db/dec_segment.map_bb.cdb
start_lab4/db/dec_segment.map_bb.hdb
start_lab4/db/dec_segment.map_bb.logdb
start_lab4/db/dec_segment.pre_map.cdb
start_lab4/db/dec_segment.pre_map.hdb
start_lab4/db/dec_segment.rtlv.hdb
start_lab4/db/dec_segment.rtlv_sg.cdb
start_lab4/db/dec_segment.rtlv_sg_swap.cdb
start_lab4/db/dec_segment.sgdiff.cdb
start_lab4/db/dec_segment.sgdiff.hdb
start_lab4/db/dec_segment.sld_design_entry.sci
start_lab4/db/dec_segment.sld_design_entry_dsc.sci
start_lab4/db/dec_segment.smart_action.txt
start_lab4/db/dec_segment.sta.qmsg
start_lab4/db/dec_segment.sta.rdb
start_lab4/db/dec_segment.sta_cmp.6_slow_1200mv_85c.tdb
start_lab4/db/dec_segment.syn_hier_info
start_lab4/db/dec_segment.tis_db_list.ddb
start_lab4/db/dec_segment.tiscmp.fast_1200mv_0c.ddb
start_lab4/db/dec_segment.tiscmp.slow_1200mv_0c.ddb
start_lab4/db/dec_segment.tiscmp.slow_1200mv_85c.ddb
start_lab4/db/dec_segment.tmw_info
start_lab4/db/dec_segment1.(0).cnf.cdb
start_lab4/db/dec_segment1.(0).cnf.hdb
start_lab4/db/dec_segment1.asm.qmsg
start_lab4/db/dec_segment1.asm.rdb
start_lab4/db/dec_segment1.asm_labs.ddb
start_lab4/db/dec_segment1.cbx.xml
start_lab4/db/dec_segment1.cmp.bpm
start_lab4/db/dec_segment1.cmp.cdb
start_lab4/db/dec_segment1.cmp.ecobp
start_lab4/db/dec_segment1.cmp.hdb
start_lab4/db/dec_segment1.cmp.kpt
start_lab4/db/dec_segment1.cmp.logdb
start_lab4/db/dec_segment1.cmp.rdb
start_lab4/db/dec_segment1.cmp_merge.kpt
start_lab4/db/dec_segment1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
start_lab4/db/dec_segment1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
start_lab4/db/dec_segment1.db_info
start_lab4/db/dec_segment1.eco.cdb
start_lab4/db/dec_segment1.fit.qmsg
start_lab4/db/dec_segment1.hier_info
start_lab4/db/dec_segment1.hif
start_lab4/db/dec_segment1.lpc.html
start_lab4/db/dec_segment1.lpc.rdb
start_lab4/db/dec_segment1.lpc.txt
start_lab4/db/dec_segment1.map.bpm
start_lab4/db/dec_segment1.map.cdb
start_lab4/db/dec_segment1.map.ecobp
start_lab4/db/dec_segment1.map.hdb
start_lab4/db/dec_segment1.map.kpt
start_lab4/db/dec_segment1.map.logdb
start_lab4/db/dec_segment1.map.qmsg
start_lab4/db/dec_segment1.map_bb.cdb
start_lab4/db/dec_segment1.map_bb.hdb
start_lab4/db/dec_segment1.map_bb.logdb
start_lab4/db/dec_segment1.pre_map.cdb
start_lab4/db/dec_segment1.pre_map.hdb
start_lab4/db/dec_segment1.rtlv.hdb
start_lab4/db/dec_segment1.rtlv_sg.cdb
start_lab4/db/dec_segment1.rtlv_sg_swap.cdb
start_lab4/db/dec_segment1.sgdiff.cdb
start_lab4/db/dec_segment1.sgdiff.hdb
start_lab4/db/dec_segment1.sld_design_entry.sci
start_lab4/db/dec_segment1.sld_design_entry_dsc.sci
start_lab4/db/dec_segment1.smart_action.txt
start_lab4/db/dec_segment1.sta.qmsg
start_lab4/db/dec_segment1.sta.rdb
start_lab4/db/dec_segment1.sta_cmp.6_slow_1200mv_85c.tdb
start_lab4/db/dec_segment1.syn_hier_info
start_lab4/db/dec_segment1.tis_db_list.ddb
start_lab4/db/dec_segment1.tiscmp.fast_1200mv_0c.ddb
start_lab4/db/dec_segment1.tiscmp.slow_1200mv_0c.ddb
start_lab4/db/dec_segment1.tiscmp.slow_1200mv_85c.ddb
start_lab4/db/dec_segment2.(0).cnf.cdb
start_lab4/db/dec_segment2.(0).cnf.hdb
start_lab4/db/dec_segment2.asm.qmsg
start_lab4/db/dec_segment2.asm.rdb
start_lab4/db/dec_segment2.asm_labs.ddb
start_lab4/db/dec_segment2.cbx.xml
start_lab4/db/dec_segment2.cmp.bpm
start_lab4/db/dec_segment2.cmp.cdb
start_lab4/db/dec_segment2.cmp.ecobp
start_lab4/db/dec_segment2.cmp.hdb
start_lab4/db/dec_segment2.cmp.kpt
start_lab4/db/dec_segment2.cmp.logdb
start_lab4/db/dec_segment2.cmp.rdb
start_lab4/db/dec_segment2.cmp_merge.kpt
start_lab4/db/dec_segment2.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hs

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