project_18_sobel/
project_18_sobel/ALINX3402.tcl
project_18_sobel/ALINX3402_EP4CE15F23C8 .tcl
project_18_sobel/ALINX3402_EP4CE30F23C6.tcl
project_18_sobel/ddr2_phy_autodetectedpins.tcl
project_18_sobel/ddr2_phy_summary.csv
project_18_sobel/ip_core/
project_18_sobel/ip_core/ddr/
project_18_sobel/ip_core/ddr/altmemphy-library/
project_18_sobel/ip_core/ddr/altmemphy-library/auk_ddr_hp_controller.ocp
project_18_sobel/ip_core/ddr/alt_mem_ddrx_addr_cmd.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_addr_cmd_wrap.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_arbiter.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_buffer.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_buffer_manager.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_burst_gen.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_burst_tracking.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_cmd_gen.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_controller.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_controller_st_top.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_csr.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_dataid_manager.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ddr2_odt_gen.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ddr3_odt_gen.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_define.iv
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_decoder.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_decoder_32_syn.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_decoder_64_syn.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_encoder.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_encoder_32_syn.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_encoder_64_syn.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_fifo.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_input_if.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_list.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_lpddr2_addr_cmd.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_mm_st_converter.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_odt_gen.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_rank_timer.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_rdata_path.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_rdwr_data_tmg.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_sideband.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_tbp.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_timing_param.v
project_18_sobel/ip_core/ddr/alt_mem_ddrx_wdata_path.v
project_18_sobel/ip_core/ddr/alt_mem_phy_defines.v
project_18_sobel/ip_core/ddr/ddr2.bsf
project_18_sobel/ip_core/ddr/ddr2.html
project_18_sobel/ip_core/ddr/ddr2.qip
project_18_sobel/ip_core/ddr/ddr2.v
project_18_sobel/ip_core/ddr/ddr2_advisor.ipa
project_18_sobel/ip_core/ddr/ddr2_alt_mem_ddrx_controller_top.v
project_18_sobel/ip_core/ddr/ddr2_bb.v
project_18_sobel/ip_core/ddr/ddr2_controller_phy.v
project_18_sobel/ip_core/ddr/ddr2_example_driver.v
project_18_sobel/ip_core/ddr/ddr2_example_top.sdc
project_18_sobel/ip_core/ddr/ddr2_example_top.v
project_18_sobel/ip_core/ddr/ddr2_ex_lfsr8.v
project_18_sobel/ip_core/ddr/ddr2_high_performance_controller-library/
project_18_sobel/ip_core/ddr/ddr2_high_performance_controller-library/auk_ddr_hp_controller.ocp
project_18_sobel/ip_core/ddr/ddr2_phy.bsf
project_18_sobel/ip_core/ddr/ddr2_phy.html
project_18_sobel/ip_core/ddr/ddr2_phy.qip
project_18_sobel/ip_core/ddr/ddr2_phy.v
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy.v
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.qip
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.v
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy_pll_bb.v
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy_seq.vhd
project_18_sobel/ip_core/ddr/ddr2_phy_alt_mem_phy_seq_wrapper.v
project_18_sobel/ip_core/ddr/ddr2_phy_autodetectedpins.tcl
project_18_sobel/ip_core/ddr/ddr2_phy_bb.v
project_18_sobel/ip_core/ddr/ddr2_phy_ddr_pins.tcl
project_18_sobel/ip_core/ddr/ddr2_phy_ddr_timing.sdc
project_18_sobel/ip_core/ddr/ddr2_phy_ddr_timing.tcl
project_18_sobel/ip_core/ddr/ddr2_phy_report_timing.tcl
project_18_sobel/ip_core/ddr/ddr2_phy_report_timing_core.tcl
project_18_sobel/ip_core/ddr/ddr2_pin_assignments.tcl
project_18_sobel/ip_core/ddr/Tcl_script1.tcl
project_18_sobel/ip_core/ddr/testbench/
project_18_sobel/ip_core/ddr/testbench/ddr2_example_top_tb.v
project_18_sobel/ip_core/ddr/testbench/ddr2_full_mem_model.v
project_18_sobel/ip_core/ddr/testbench/ddr2_mem_model.v
project_18_sobel/PLLJ_PLLSPE_INFO.txt
project_18_sobel/src/
project_18_sobel/src/bt656_decode.v
project_18_sobel/src/bt656_rec.v
project_18_sobel/src/calu.v
project_18_sobel/src/demux.v
project_18_sobel/src/fifo/
project_18_sobel/src/fifo/fifo_1024_16.v
project_18_sobel/src/fifo/fifo_128_16.v
project_18_sobel/src/fifo/fifo_2048_16.v
project_18_sobel/src/fifo/fifo_256_16.v
project_18_sobel/src/fifo/fifo_256_32.v
project_18_sobel/src/fifo/fifo_256_32i_16o.v
project_18_sobel/src/fifo/fifo_256_64.v
project_18_sobel/src/fifo/fifo_256_64i_16o.v
project_18_sobel/src/fifo/fifo_32_24.v
project_18_sobel/src/fifo/fifo_4096_16.v
project_18_sobel/src/fifo/fifo_4096_24.v
project_18_sobel/src/fifo/fifo_512_16.v
project_18_sobel/src/fifo/fifo_512_24.v
project_18_sobel/src/fifo/fifo_512_3