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文件名称:project_14_4D1_VGA

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  • 上传时间:
    2014-12-10
  • 文件大小:
    5.96mb
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    0次
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VGA显示在现代的多媒体时代显得非常重要,这是人们获取信息的重要途径-VGA display in the modern era of multimedia is very important, it is an important way for people to obtain information
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下载文件列表

project_14_4D1_VGA/
project_14_4D1_VGA/ALINX3402.tcl
project_14_4D1_VGA/ALINX3402_EP4CE15F23C8 .tcl
project_14_4D1_VGA/ALINX3402_EP4CE30F23C6.tcl
project_14_4D1_VGA/ddr2.xml
project_14_4D1_VGA/ddr2_phy_autodetectedpins.tcl
project_14_4D1_VGA/ddr2_phy_summary.csv
project_14_4D1_VGA/fifo_512_16.qip
project_14_4D1_VGA/greybox_tmp/
project_14_4D1_VGA/greybox_tmp/cbx_args.txt
project_14_4D1_VGA/ip_core/
project_14_4D1_VGA/ip_core/ddr/
project_14_4D1_VGA/ip_core/ddr/altmemphy-library/
project_14_4D1_VGA/ip_core/ddr/altmemphy-library/auk_ddr_hp_controller.ocp
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_addr_cmd.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_addr_cmd_wrap.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_arbiter.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_buffer.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_buffer_manager.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_burst_gen.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_burst_tracking.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_cmd_gen.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_controller.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_controller_st_top.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_csr.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_dataid_manager.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ddr2_odt_gen.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ddr3_odt_gen.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_define.iv
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_decoder.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_decoder_32_syn.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_decoder_64_syn.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_encoder.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_encoder_32_syn.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_encoder_64_syn.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_fifo.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_input_if.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_list.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_lpddr2_addr_cmd.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_mm_st_converter.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_odt_gen.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_rank_timer.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_rdata_path.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_rdwr_data_tmg.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_sideband.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_tbp.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_timing_param.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_ddrx_wdata_path.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_phy_defines.v
project_14_4D1_VGA/ip_core/ddr/alt_mem_phy_sequencer.vhd
project_14_4D1_VGA/ip_core/ddr/auk_ddr_hp_controller.ocp
project_14_4D1_VGA/ip_core/ddr/auk_ddr_hp_controller.vhd
project_14_4D1_VGA/ip_core/ddr/ddr2.bsf
project_14_4D1_VGA/ip_core/ddr/ddr2.html
project_14_4D1_VGA/ip_core/ddr/ddr2.ppf
project_14_4D1_VGA/ip_core/ddr/ddr2.qip
project_14_4D1_VGA/ip_core/ddr/ddr2.v
project_14_4D1_VGA/ip_core/ddr/ddr2.v.bak
project_14_4D1_VGA/ip_core/ddr/ddr2_advisor.ipa
project_14_4D1_VGA/ip_core/ddr/ddr2_alt_mem_ddrx_controller_top.v
project_14_4D1_VGA/ip_core/ddr/ddr2_auk_ddr_hp_controller_wrapper.v
project_14_4D1_VGA/ip_core/ddr/ddr2_bb.v
project_14_4D1_VGA/ip_core/ddr/ddr2_controller_phy.v
project_14_4D1_VGA/ip_core/ddr/ddr2_example_driver.v
project_14_4D1_VGA/ip_core/ddr/ddr2_example_top.sdc
project_14_4D1_VGA/ip_core/ddr/ddr2_example_top.v
project_14_4D1_VGA/ip_core/ddr/ddr2_example_top.v.bak
project_14_4D1_VGA/ip_core/ddr/ddr2_example_top.v.tmp2
project_14_4D1_VGA/ip_core/ddr/ddr2_ex_lfsr8.v
project_14_4D1_VGA/ip_core/ddr/ddr2_high_performance_controller-library/
project_14_4D1_VGA/ip_core/ddr/ddr2_high_performance_controller-library/auk_ddr_hp_controller.ocp
project_14_4D1_VGA/ip_core/ddr/ddr2_phy.bsf
project_14_4D1_VGA/ip_core/ddr/ddr2_phy.html
project_14_4D1_VGA/ip_core/ddr/ddr2_phy.qip
project_14_4D1_VGA/ip_core/ddr/ddr2_phy.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.ppf
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.qip
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_pll.v_.bak
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_pll_bb.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_seq.vhd
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_sequencer_wrapper.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_alt_mem_phy_seq_wrapper.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_autodetectedpins.tcl
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_bb.v
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_ddr_pins.tcl
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_ddr_timing.sdc
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_ddr_timing.tcl
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_report_timing.tcl
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_report_timing_core.tcl
project_14_4D1_VGA/ip_core/ddr/ddr2_phy_summary.csv
project_14_4D1_VGA/ip_core/ddr/ddr2_pin_assignments.tcl
project_14_4D1_VGA/ip_core/ddr/greybox_tmp/
project_14_4D1_VGA/ip_core/dd

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