文件名称:uart_verilog
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- 上传时间:2014-12-13
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文件大小:2.59mb
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用verilog实现串口通信,实现串口的接收及发送。-Using Verilog serial communication, the realization of sending and receiving serial.
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下载文件列表
uart_verilog/
uart_verilog/modelsim/
uart_verilog/modelsim/uart.cr.mti
uart_verilog/modelsim/uart.mpf
uart_verilog/modelsim/vsim.wlf
uart_verilog/modelsim/wave.bmp
uart_verilog/modelsim/work/
uart_verilog/modelsim/work/uart/
uart_verilog/modelsim/work/uart/verilog.asm
uart_verilog/modelsim/work/uart/_primary.dat
uart_verilog/modelsim/work/uart/_primary.vhd
uart_verilog/modelsim/work/uart_rx/
uart_verilog/modelsim/work/uart_rx/verilog.asm
uart_verilog/modelsim/work/uart_rx/_primary.dat
uart_verilog/modelsim/work/uart_rx/_primary.vhd
uart_verilog/modelsim/work/uart_tb/
uart_verilog/modelsim/work/uart_tb/verilog.asm
uart_verilog/modelsim/work/uart_tb/_primary.dat
uart_verilog/modelsim/work/uart_tb/_primary.vhd
uart_verilog/modelsim/work/uart_tx/
uart_verilog/modelsim/work/uart_tx/verilog.asm
uart_verilog/modelsim/work/uart_tx/_primary.dat
uart_verilog/modelsim/work/uart_tx/_primary.vhd
uart_verilog/modelsim/work/_info
uart_verilog/modelsim/work/_temp/
uart_verilog/quartus/
uart_verilog/quartus/db/
uart_verilog/quartus/db/logic_util_heursitic.dat
uart_verilog/quartus/db/prev_cmp_uart.asm.qmsg
uart_verilog/quartus/db/prev_cmp_uart.fit.qmsg
uart_verilog/quartus/db/prev_cmp_uart.map.qmsg
uart_verilog/quartus/db/prev_cmp_uart.qmsg
uart_verilog/quartus/db/prev_cmp_uart.sta.qmsg
uart_verilog/quartus/db/uart.(0).cnf.cdb
uart_verilog/quartus/db/uart.(0).cnf.hdb
uart_verilog/quartus/db/uart.(1).cnf.cdb
uart_verilog/quartus/db/uart.(1).cnf.hdb
uart_verilog/quartus/db/uart.(2).cnf.cdb
uart_verilog/quartus/db/uart.(2).cnf.hdb
uart_verilog/quartus/db/uart.(3).cnf.cdb
uart_verilog/quartus/db/uart.(3).cnf.hdb
uart_verilog/quartus/db/uart.amm.cdb
uart_verilog/quartus/db/uart.asm.qmsg
uart_verilog/quartus/db/uart.asm.rdb
uart_verilog/quartus/db/uart.asm_labs.ddb
uart_verilog/quartus/db/uart.cbx.xml
uart_verilog/quartus/db/uart.cmp.bpm
uart_verilog/quartus/db/uart.cmp.cdb
uart_verilog/quartus/db/uart.cmp.hdb
uart_verilog/quartus/db/uart.cmp.kpt
uart_verilog/quartus/db/uart.cmp.logdb
uart_verilog/quartus/db/uart.cmp.rdb
uart_verilog/quartus/db/uart.cmp2.ddb
uart_verilog/quartus/db/uart.cmp_merge.kpt
uart_verilog/quartus/db/uart.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
uart_verilog/quartus/db/uart.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
uart_verilog/quartus/db/uart.db_info
uart_verilog/quartus/db/uart.fit.qmsg
uart_verilog/quartus/db/uart.hier_info
uart_verilog/quartus/db/uart.hif
uart_verilog/quartus/db/uart.idb.cdb
uart_verilog/quartus/db/uart.lpc.html
uart_verilog/quartus/db/uart.lpc.rdb
uart_verilog/quartus/db/uart.lpc.txt
uart_verilog/quartus/db/uart.map.bpm
uart_verilog/quartus/db/uart.map.cdb
uart_verilog/quartus/db/uart.map.hdb
uart_verilog/quartus/db/uart.map.kpt
uart_verilog/quartus/db/uart.map.logdb
uart_verilog/quartus/db/uart.map.qmsg
uart_verilog/quartus/db/uart.map_bb.cdb
uart_verilog/quartus/db/uart.map_bb.hdb
uart_verilog/quartus/db/uart.map_bb.logdb
uart_verilog/quartus/db/uart.pre_map.cdb
uart_verilog/quartus/db/uart.pre_map.hdb
uart_verilog/quartus/db/uart.rpp.qmsg
uart_verilog/quartus/db/uart.rtlv.hdb
uart_verilog/quartus/db/uart.rtlv_sg.cdb
uart_verilog/quartus/db/uart.rtlv_sg_swap.cdb
uart_verilog/quartus/db/uart.sgate.rvd
uart_verilog/quartus/db/uart.sgate_sm.rvd
uart_verilog/quartus/db/uart.sgdiff.cdb
uart_verilog/quartus/db/uart.sgdiff.hdb
uart_verilog/quartus/db/uart.sld_design_entry.sci
uart_verilog/quartus/db/uart.sld_design_entry_dsc.sci
uart_verilog/quartus/db/uart.smart_action.txt
uart_verilog/quartus/db/uart.smp_dump.txt
uart_verilog/quartus/db/uart.sta.qmsg
uart_verilog/quartus/db/uart.sta.rdb
uart_verilog/quartus/db/uart.sta_cmp.8_slow_1200mv_85c.tdb
uart_verilog/quartus/db/uart.syn_hier_info
uart_verilog/quartus/db/uart.tiscmp.fast_1200mv_0c.ddb
uart_verilog/quartus/db/uart.tiscmp.slow_1200mv_0c.ddb
uart_verilog/quartus/db/uart.tiscmp.slow_1200mv_85c.ddb
uart_verilog/quartus/db/uart.tis_db_list.ddb
uart_verilog/quartus/db/uart_global_asgn_op.abo
uart_verilog/quartus/incremental_db/
uart_verilog/quartus/incremental_db/compiled_partitions/
uart_verilog/quartus/incremental_db/compiled_partitions/uart.db_info
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.cdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.hdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.rcfdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.atm
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.cdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.dpi
uart
uart_verilog/modelsim/
uart_verilog/modelsim/uart.cr.mti
uart_verilog/modelsim/uart.mpf
uart_verilog/modelsim/vsim.wlf
uart_verilog/modelsim/wave.bmp
uart_verilog/modelsim/work/
uart_verilog/modelsim/work/uart/
uart_verilog/modelsim/work/uart/verilog.asm
uart_verilog/modelsim/work/uart/_primary.dat
uart_verilog/modelsim/work/uart/_primary.vhd
uart_verilog/modelsim/work/uart_rx/
uart_verilog/modelsim/work/uart_rx/verilog.asm
uart_verilog/modelsim/work/uart_rx/_primary.dat
uart_verilog/modelsim/work/uart_rx/_primary.vhd
uart_verilog/modelsim/work/uart_tb/
uart_verilog/modelsim/work/uart_tb/verilog.asm
uart_verilog/modelsim/work/uart_tb/_primary.dat
uart_verilog/modelsim/work/uart_tb/_primary.vhd
uart_verilog/modelsim/work/uart_tx/
uart_verilog/modelsim/work/uart_tx/verilog.asm
uart_verilog/modelsim/work/uart_tx/_primary.dat
uart_verilog/modelsim/work/uart_tx/_primary.vhd
uart_verilog/modelsim/work/_info
uart_verilog/modelsim/work/_temp/
uart_verilog/quartus/
uart_verilog/quartus/db/
uart_verilog/quartus/db/logic_util_heursitic.dat
uart_verilog/quartus/db/prev_cmp_uart.asm.qmsg
uart_verilog/quartus/db/prev_cmp_uart.fit.qmsg
uart_verilog/quartus/db/prev_cmp_uart.map.qmsg
uart_verilog/quartus/db/prev_cmp_uart.qmsg
uart_verilog/quartus/db/prev_cmp_uart.sta.qmsg
uart_verilog/quartus/db/uart.(0).cnf.cdb
uart_verilog/quartus/db/uart.(0).cnf.hdb
uart_verilog/quartus/db/uart.(1).cnf.cdb
uart_verilog/quartus/db/uart.(1).cnf.hdb
uart_verilog/quartus/db/uart.(2).cnf.cdb
uart_verilog/quartus/db/uart.(2).cnf.hdb
uart_verilog/quartus/db/uart.(3).cnf.cdb
uart_verilog/quartus/db/uart.(3).cnf.hdb
uart_verilog/quartus/db/uart.amm.cdb
uart_verilog/quartus/db/uart.asm.qmsg
uart_verilog/quartus/db/uart.asm.rdb
uart_verilog/quartus/db/uart.asm_labs.ddb
uart_verilog/quartus/db/uart.cbx.xml
uart_verilog/quartus/db/uart.cmp.bpm
uart_verilog/quartus/db/uart.cmp.cdb
uart_verilog/quartus/db/uart.cmp.hdb
uart_verilog/quartus/db/uart.cmp.kpt
uart_verilog/quartus/db/uart.cmp.logdb
uart_verilog/quartus/db/uart.cmp.rdb
uart_verilog/quartus/db/uart.cmp2.ddb
uart_verilog/quartus/db/uart.cmp_merge.kpt
uart_verilog/quartus/db/uart.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
uart_verilog/quartus/db/uart.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
uart_verilog/quartus/db/uart.db_info
uart_verilog/quartus/db/uart.fit.qmsg
uart_verilog/quartus/db/uart.hier_info
uart_verilog/quartus/db/uart.hif
uart_verilog/quartus/db/uart.idb.cdb
uart_verilog/quartus/db/uart.lpc.html
uart_verilog/quartus/db/uart.lpc.rdb
uart_verilog/quartus/db/uart.lpc.txt
uart_verilog/quartus/db/uart.map.bpm
uart_verilog/quartus/db/uart.map.cdb
uart_verilog/quartus/db/uart.map.hdb
uart_verilog/quartus/db/uart.map.kpt
uart_verilog/quartus/db/uart.map.logdb
uart_verilog/quartus/db/uart.map.qmsg
uart_verilog/quartus/db/uart.map_bb.cdb
uart_verilog/quartus/db/uart.map_bb.hdb
uart_verilog/quartus/db/uart.map_bb.logdb
uart_verilog/quartus/db/uart.pre_map.cdb
uart_verilog/quartus/db/uart.pre_map.hdb
uart_verilog/quartus/db/uart.rpp.qmsg
uart_verilog/quartus/db/uart.rtlv.hdb
uart_verilog/quartus/db/uart.rtlv_sg.cdb
uart_verilog/quartus/db/uart.rtlv_sg_swap.cdb
uart_verilog/quartus/db/uart.sgate.rvd
uart_verilog/quartus/db/uart.sgate_sm.rvd
uart_verilog/quartus/db/uart.sgdiff.cdb
uart_verilog/quartus/db/uart.sgdiff.hdb
uart_verilog/quartus/db/uart.sld_design_entry.sci
uart_verilog/quartus/db/uart.sld_design_entry_dsc.sci
uart_verilog/quartus/db/uart.smart_action.txt
uart_verilog/quartus/db/uart.smp_dump.txt
uart_verilog/quartus/db/uart.sta.qmsg
uart_verilog/quartus/db/uart.sta.rdb
uart_verilog/quartus/db/uart.sta_cmp.8_slow_1200mv_85c.tdb
uart_verilog/quartus/db/uart.syn_hier_info
uart_verilog/quartus/db/uart.tiscmp.fast_1200mv_0c.ddb
uart_verilog/quartus/db/uart.tiscmp.slow_1200mv_0c.ddb
uart_verilog/quartus/db/uart.tiscmp.slow_1200mv_85c.ddb
uart_verilog/quartus/db/uart.tis_db_list.ddb
uart_verilog/quartus/db/uart_global_asgn_op.abo
uart_verilog/quartus/incremental_db/
uart_verilog/quartus/incremental_db/compiled_partitions/
uart_verilog/quartus/incremental_db/compiled_partitions/uart.db_info
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.cdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.hdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.cmp.rcfdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.atm
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.cdb
uart_verilog/quartus/incremental_db/compiled_partitions/uart.root_partition.map.dpi
uart
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