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文件名称:ck1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Windows] [程序]
  • 上传时间：
    2014-12-16
  • 文件大小：
    524.73kb
  • 已下载：
    0次
  • 提 供 者：
    m*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用FPGA实现的数码管时钟，使用的是Nexys4开发板，所以使用了视觉暂留原理实现数码管的显示。-FPGA implementation with digital clock, using Nexys4 development board, so the use of the principle of persistence of vision to realize digital tube display.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ck1/ck.cache/wt/java_command_handlers.wdf
ck1/ck.cache/wt/synthesis.wdf
ck1/ck.cache/wt/webtalk_pa.xml
ck1/ck.cache/wt/xsim.wdf
ck1/ck.ioplanning/constrs_1/designprops.xml
ck1/ck.ioplanning/constrs_1/usercols.xml
ck1/ck.runs/.jobs/vrs_config_1.xml
ck1/ck.runs/.jobs/vrs_config_2.xml
ck1/ck.runs/.jobs/vrs_config_3.xml
ck1/ck.runs/.jobs/vrs_config_4.xml
ck1/ck.runs/.jobs/vrs_config_5.xml
ck1/ck.runs/.jobs/vrs_config_6.xml
ck1/ck.runs/impl_1/.init_design.begin.rst
ck1/ck.runs/impl_1/.init_design.end.rst
ck1/ck.runs/impl_1/.opt_design.begin.rst
ck1/ck.runs/impl_1/.opt_design.end.rst
ck1/ck.runs/impl_1/.place_design.begin.rst
ck1/ck.runs/impl_1/.place_design.end.rst
ck1/ck.runs/impl_1/.route_design.begin.rst
ck1/ck.runs/impl_1/.route_design.end.rst
ck1/ck.runs/impl_1/.Vivado Implementation.queue.rst
ck1/ck.runs/impl_1/.vivado.begin.rst
ck1/ck.runs/impl_1/.vivado.end.rst
ck1/ck.runs/impl_1/.write_bitstream.begin.rst
ck1/ck.runs/impl_1/.write_bitstream.end.rst
ck1/ck.runs/impl_1/clock.bit
ck1/ck.runs/impl_1/clock.tcl
ck1/ck.runs/impl_1/clock.vdi
ck1/ck.runs/impl_1/clock_clock_utilization_placed.rpt
ck1/ck.runs/impl_1/clock_control_sets_placed.rpt
ck1/ck.runs/impl_1/clock_drc_routed.pb
ck1/ck.runs/impl_1/clock_drc_routed.rpt
ck1/ck.runs/impl_1/clock_io_placed.rpt
ck1/ck.runs/impl_1/clock_opt.dcp
ck1/ck.runs/impl_1/clock_placed.dcp
ck1/ck.runs/impl_1/clock_power_routed.rpt
ck1/ck.runs/impl_1/clock_power_summary_routed.pb
ck1/ck.runs/impl_1/clock_routed.dcp
ck1/ck.runs/impl_1/clock_route_status.pb
ck1/ck.runs/impl_1/clock_route_status.rpt
ck1/ck.runs/impl_1/clock_timing_summary_routed.pb
ck1/ck.runs/impl_1/clock_timing_summary_routed.rpt
ck1/ck.runs/impl_1/clock_utilization_placed.pb
ck1/ck.runs/impl_1/clock_utilization_placed.rpt
ck1/ck.runs/impl_1/gen_run.xml
ck1/ck.runs/impl_1/htr.txt
ck1/ck.runs/impl_1/init_design.pb
ck1/ck.runs/impl_1/ISEWrap.js
ck1/ck.runs/impl_1/ISEWrap.sh
ck1/ck.runs/impl_1/opt_design.pb
ck1/ck.runs/impl_1/place_design.pb
ck1/ck.runs/impl_1/project.wdf
ck1/ck.runs/impl_1/route_design.pb
ck1/ck.runs/impl_1/rundef.js
ck1/ck.runs/impl_1/runme.bat
ck1/ck.runs/impl_1/runme.log
ck1/ck.runs/impl_1/runme.sh
ck1/ck.runs/impl_1/usage_statistics_webtalk.html
ck1/ck.runs/impl_1/usage_statistics_webtalk.xml
ck1/ck.runs/impl_1/vivado.jou
ck1/ck.runs/impl_1/vivado.pb
ck1/ck.runs/impl_1/write_bitstream.pb
ck1/ck.runs/synth_1/.Vivado Synthesis.queue.rst
ck1/ck.runs/synth_1/.vivado.begin.rst
ck1/ck.runs/synth_1/.vivado.end.rst
ck1/ck.runs/synth_1/clock.dcp
ck1/ck.runs/synth_1/clock.tcl
ck1/ck.runs/synth_1/clock.vds
ck1/ck.runs/synth_1/clock_utilization_synth.pb
ck1/ck.runs/synth_1/clock_utilization_synth.rpt
ck1/ck.runs/synth_1/gen_run.xml
ck1/ck.runs/synth_1/htr.txt
ck1/ck.runs/synth_1/ISEWrap.js
ck1/ck.runs/synth_1/ISEWrap.sh
ck1/ck.runs/synth_1/rundef.js
ck1/ck.runs/synth_1/runme.bat
ck1/ck.runs/synth_1/runme.log
ck1/ck.runs/synth_1/runme.sh
ck1/ck.runs/synth_1/vivado.jou
ck1/ck.runs/synth_1/vivado.pb
ck1/ck.sim/sim_1/behav/compile.bat
ck1/ck.sim/sim_1/behav/compile.sh
ck1/ck.sim/sim_1/behav/test_ck.prj
ck1/ck.sim/sim_1/behav/test_ck.tcl
ck1/ck.sim/sim_1/behav/test_ck_behav.log
ck1/ck.sim/sim_1/behav/test_ck_behav.wdb
ck1/ck.sim/sim_1/behav/xelab.log
ck1/ck.sim/sim_1/behav/xelab.pb
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/Compile_Options.txt
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.dbg
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.mem
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.reloc
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.rtti
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.svtype
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.type
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsim.xdbg
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsimcrash.log
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsimk.exe
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav/xsimkernel.log
ck1/ck.sim/sim_1/behav/xsim.dir/xil_defaultlib/clock.sdb
ck1/ck.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb
ck1/ck.sim/sim_1/behav/xsim.dir/xil_defaultlib/test_ck.sdb
ck1/ck.sim/sim_1/behav/xsim.ini
ck1/ck.srcs/constrs_1/new/top_xdc.xdc
ck1/ck.srcs/sim_1/new/test_ck.v
ck1/ck.srcs/sources_1/new/ck.v
ck1/ck.xpr
ck1/ck.sim/sim_1/behav/xsim.dir/test_ck_behav
ck1/ck.sim/sim_1/behav/xsim.dir/xil_defaultlib
ck1/ck.sim/sim_1/behav/xsim.dir
ck1/ck.hw/hw_1/wave
ck1/ck.runs/impl_1/.Xil
ck1/ck.runs/synth_1/.Xil
ck1/ck.sim/sim_1/behav
ck1/ck.srcs/constrs_1/new
ck1/ck.srcs/sim_1/new
ck1/ck.srcs/sources_1/new
ck1/ck.cache/compile_simlib
ck1/ck.cache/wt
ck1/ck.data/constrs_1
ck1/ck.hw/hw_1
ck1/ck.ioplanning/constrs_1
ck1/ck.runs/.jobs
ck1/ck.runs/impl_1
ck1/ck.runs/synth_1
ck1/ck.sim/sim_1
ck1/ck.srcs/constrs_1
ck1/ck.srcs/sim_1
ck1/ck.srcs/sources_1
ck1/ck.cache
ck1/ck.data
ck1/ck.hw
ck1/ck.ioplanning
ck1/ck.runs
ck1/ck.sim
ck1/ck.srcs
ck1

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