Ex1_Multicycle/
Ex1_Multicycle/clock_enable_multicycle.bdf
Ex1_Multicycle/clock_enable_multicycle.qpf
Ex1_Multicycle/clock_enable_multicycle.qsf
Ex1_Multicycle/clock_enable_multicycle.sdc
Ex1_Multicycle/Solutions/
Ex1_Multicycle/Solutions/clock_enable_multicycle_solution.sdc
Ex2_SSI_SDR/
Ex2_SSI_SDR/Scripts/
Ex2_SSI_SDR/Scripts/input_analysis.tcl
Ex2_SSI_SDR/Scripts/output_analysis.tcl
Ex2_SSI_SDR/sfi_41.pin
Ex2_SSI_SDR/sfi_41.qpf
Ex2_SSI_SDR/sfi_41.qsf
Ex2_SSI_SDR/sfi_41.sdc
Ex2_SSI_SDR/sfi_41.sdc.bak
Ex2_SSI_SDR/sfi_41.v
Ex2_SSI_SDR/sfi_pll.ppf
Ex2_SSI_SDR/sfi_pll.qip
Ex2_SSI_SDR/sfi_pll.v
Ex2_SSI_SDR/Solutions/
Ex2_SSI_SDR/Solutions/sfi_41_solution.sdc
Ex2_SSI_SDR/Solutions/sfi_41_solution.sdc.bak
Ex2_SSI_SDR/tx_ddio_1.ppf
Ex2_SSI_SDR/tx_ddio_1.qip
Ex2_SSI_SDR/tx_ddio_1.v
Ex2_SSI_SDR/tx_ddio_16.ppf
Ex2_SSI_SDR/tx_ddio_16.qip
Ex2_SSI_SDR/tx_ddio_16.v
Ex3_SSI_DDR/
Ex3_SSI_DDR/rgmii.qpf
Ex3_SSI_DDR/rgmii.qsf
Ex3_SSI_DDR/rgmii.sdc
Ex3_SSI_DDR/rgmii.v
Ex3_SSI_DDR/rgmii_assignment_defaults.qdf
Ex3_SSI_DDR/RX_DDIO.ppf
Ex3_SSI_DDR/RX_DDIO.v
Ex3_SSI_DDR/rx_pll.ppf
Ex3_SSI_DDR/rx_pll.qip
Ex3_SSI_DDR/rx_pll.v
Ex3_SSI_DDR/Solutions/
Ex3_SSI_DDR/Solutions/rgmii_solution.sdc
Ex3_SSI_DDR/TX_DDIO.ppf
Ex3_SSI_DDR/TX_DDIO.v
Ex3_SSI_DDR/TX_DDIO_CLK.ppf
Ex3_SSI_DDR/TX_DDIO_CLK.qip
Ex3_SSI_DDR/TX_DDIO_CLK.v
Ex3_SSI_DDR/tx_pll.ppf
Ex3_SSI_DDR/tx_pll.qip
Ex3_SSI_DDR/tx_pll.v
Ex4_Feedback/
Ex4_Feedback/clock_feedback_assp.bdf
Ex4_Feedback/clock_feedback_assp.qpf
Ex4_Feedback/clock_feedback_assp.qsf
Ex4_Feedback/clock_feedback_assp.sdc
Ex4_Feedback/clock_feedback_assp_assignment_defaults.qdf
Ex4_Feedback/pll_fpga_assp.bsf
Ex4_Feedback/pll_fpga_assp.ppf
Ex4_Feedback/pll_fpga_assp.qip
Ex4_Feedback/pll_fpga_assp.v
Ex4_Feedback/pll_fpga_assp_bb.v
Ex4_Feedback/pll_fpga_assp_inst.v
Ex4_Feedback/Solutions/
Ex4_Feedback/Solutions/clock_feedback_assp_solution.sdc
Ex5_LVDS/
Ex5_LVDS/diff_io_top.qpf
Ex5_LVDS/diff_io_top.qsf
Ex5_LVDS/diff_io_top.sdc
Ex5_LVDS/diff_io_top.v
Ex5_LVDS/fir.html
Ex5_LVDS/fir.qip
Ex5_LVDS/fir.v
Ex5_LVDS/fir_ast.vhd
Ex5_LVDS/fir_coef_0.hex
Ex5_LVDS/fir_coef_0_inv.hex
Ex5_LVDS/fir_coef_1.hex
Ex5_LVDS/fir_coef_1_inv.hex
Ex5_LVDS/fir_compiler-library/
Ex5_LVDS/fir_compiler-library/accum.v
Ex5_LVDS/fir_compiler-library/addr_cnt_dn.v
Ex5_LVDS/fir_compiler-library/addr_cnt_dn_poly.v
Ex5_LVDS/fir_compiler-library/addr_cnt_up.v
Ex5_LVDS/fir_compiler-library/at_sink_mod.v
Ex5_LVDS/fir_compiler-library/at_sink_mod_bin.v
Ex5_LVDS/fir_compiler-library/at_sink_mod_par.v
Ex5_LVDS/fir_compiler-library/at_src_mod.v
Ex5_LVDS/fir_compiler-library/at_src_mod_par.v
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_block_sink_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_block_source_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_controller_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_controller_pe_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_monitor_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_100.ocp
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_sink_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_sink_model_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_source_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_source_from_monitor_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_avalon_streaming_source_model_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_delay_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fast_accumulator_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fastadd_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fastaddsub_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fifo_pfc_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_accumulator_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_adder_tree_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_adders_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_avalon_slave_write_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_coef_banks_fixed_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_data_memory_bank_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_dspblock_bank_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_dspblock_cascade_bank_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_lib_pkg_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_math_pkg_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_memory_simple_dual_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_memory_single_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_memory_true_dual_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_mult_bank_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_top_dec_half_sym_fir_100.ocp
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_top_dec_half_sym_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_top_dec_sym_add_cas_fir_100.vhd
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_top_dec_sym_cas_fir_100.ocp
Ex5_LVDS/fir_compiler-library/auk_dspip_fir_top_int_sym_fir_100.ocp
Ex5_LV