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文件名称:ROM_test

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-01-03
  • 文件大小：
    165.85kb
  • 已下载：
    0次
  • 提 供 者：
    苏****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

测试ROM的例子用Verilog写的，里面有测试文件，测试通过完全可用！-Examples of test ROM data
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K.gen
ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K.log
ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K.v
ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K.shx
ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K_R0C0.mem
ROM_test/ROM_test/smartgen/ROM_2K/ROM_2K.cxf
ROM_test/ROM_test/smartgen/smartgen.aws
ROM_test/ROM_test/smartgen/ROM_2K_work.ixf
ROM_test/ROM_test/hdl/C51_LED.HEX
ROM_test/ROM_test/hdl/ROMX.HEX
ROM_test/ROM_test/hdl/ROM_test.v
ROM_test/ROM_test/viewdraw/vf/project.lst
ROM_test/ROM_test/viewdraw/viewdraw.ini
ROM_test/ROM_test/simulation/run.do
ROM_test/ROM_test/simulation/modelsim.log
ROM_test/ROM_test/simulation/postsynth/_info
ROM_test/ROM_test/simulation/postsynth/_temp/vlogmdytfa
ROM_test/ROM_test/simulation/postsynth/_temp/vloghhjese
ROM_test/ROM_test/simulation/postsynth/_vmake
ROM_test/ROM_test/simulation/postsynth/@r@o@m_2@k/_primary.vhd
ROM_test/ROM_test/simulation/postsynth/@r@o@m_2@k/verilog.psm
ROM_test/ROM_test/simulation/postsynth/@r@o@m_2@k/_primary.dbs
ROM_test/ROM_test/simulation/postsynth/@r@o@m_2@k/_primary.dat
ROM_test/ROM_test/simulation/postsynth/@r@o@m_test/_primary.vhd
ROM_test/ROM_test/simulation/postsynth/@r@o@m_test/verilog.psm
ROM_test/ROM_test/simulation/postsynth/@r@o@m_test/_primary.dbs
ROM_test/ROM_test/simulation/postsynth/@r@o@m_test/_primary.dat
ROM_test/ROM_test/simulation/postsynth/testbench/_primary.vhd
ROM_test/ROM_test/simulation/postsynth/testbench/verilog.psm
ROM_test/ROM_test/simulation/postsynth/testbench/_primary.dbs
ROM_test/ROM_test/simulation/postsynth/testbench/_primary.dat
ROM_test/ROM_test/simulation/vsim.wlf
ROM_test/ROM_test/simulation/wave.do
ROM_test/ROM_test/simulation/modelsim.ini.sav
ROM_test/ROM_test/simulation/presynth/_info
ROM_test/ROM_test/simulation/presynth/_vmake
ROM_test/ROM_test/simulation/presynth/@r@o@m_2@k/_primary.vhd
ROM_test/ROM_test/simulation/presynth/@r@o@m_2@k/verilog.psm
ROM_test/ROM_test/simulation/presynth/@r@o@m_2@k/_primary.dbs
ROM_test/ROM_test/simulation/presynth/@r@o@m_2@k/_primary.dat
ROM_test/ROM_test/simulation/presynth/@r@o@m_test/_primary.vhd
ROM_test/ROM_test/simulation/presynth/@r@o@m_test/verilog.psm
ROM_test/ROM_test/simulation/presynth/@r@o@m_test/_primary.dbs
ROM_test/ROM_test/simulation/presynth/@r@o@m_test/_primary.dat
ROM_test/ROM_test/simulation/presynth/testbench/_primary.vhd
ROM_test/ROM_test/simulation/presynth/testbench/verilog.psm
ROM_test/ROM_test/simulation/presynth/testbench/_primary.dbs
ROM_test/ROM_test/simulation/presynth/testbench/_primary.dat
ROM_test/ROM_test/simulation/modelsim.ini
ROM_test/ROM_test/simulation/ROM_2K_R0C0.mem
ROM_test/ROM_test/synthesis/stdout.log
ROM_test/ROM_test/synthesis/syntmp/ROM_test_flink.htm
ROM_test/ROM_test/synthesis/syntmp/ROM_test_srr.htm
ROM_test/ROM_test/synthesis/syntmp/ROM_test_toc.htm
ROM_test/ROM_test/synthesis/syntmp/sap.log
ROM_test/ROM_test/synthesis/syntmp/ROM_test.plg
ROM_test/ROM_test/synthesis/backup/ROM_test.srr
ROM_test/ROM_test/synthesis/run_options.txt
ROM_test/ROM_test/synthesis/ROM_test.htm
ROM_test/ROM_test/synthesis/ROM_test.tlg
ROM_test/ROM_test/synthesis/ROM_test.sap
ROM_test/ROM_test/synthesis/ROM_test.fse
ROM_test/ROM_test/synthesis/ROM_test.szr
ROM_test/ROM_test/synthesis/ROM_test.srd
ROM_test/ROM_test/synthesis/ROM_test.srm
ROM_test/ROM_test/synthesis/ROM_test.map
ROM_test/ROM_test/synthesis/ROM_test.edn
ROM_test/ROM_test/synthesis/ROM_test.sdf
ROM_test/ROM_test/synthesis/ROM_test.pdc
ROM_test/ROM_test/synthesis/ROM_test_sdc.sdc
ROM_test/ROM_test/synthesis/ROM_test.so
ROM_test/ROM_test/synthesis/ROM_test.areasrr
ROM_test/ROM_test/synthesis/ROM_test.v
ROM_test/ROM_test/synthesis/synthesis_identify/syntmp/ROM_test_flink.htm
ROM_test/ROM_test/synthesis/synthesis_identify/ROM_test.srs
ROM_test/ROM_test/synthesis/synthesis_identify/ROM_test.tlg
ROM_test/ROM_test/synthesis/ROM_test_syn.prj
ROM_test/ROM_test/synthesis/ROM_test.srr
ROM_test/ROM_test/synthesis/ROM_test.srs
ROM_test/ROM_test/stimulus/testbench.v
ROM_test/ROM_test/designer/impl1/count4.ide_des
ROM_test/ROM_test/designer/impl1/F161xb8.ide_des
ROM_test/ROM_test/designer/impl1/ROM_test.ide_des
ROM_test/ROM_test/designer/impl1/ROM_2K.ide_des
ROM_test/ROM_test/designer/impl1/ROM_test.tcl
ROM_test/ROM_test/designer/impl1/designer_synth_check.log
ROM_test/ROM_test/designer/impl1/ROM_test.adb
ROM_test/ROM_test/designer/impl1/designer.log
ROM_test/ROM_test/ROM_test.prj
ROM_test/ROM_test/simulation/postsynth/_temp
ROM_test/ROM_test/simulation/postsynth/@r@o@m_2@k
ROM_test/ROM_test/simulation/postsynth/@r@o@m_test
ROM_test/ROM_test/simulation/postsynth/testbench
ROM_test/ROM_test/simulation/presynth/_temp
ROM_test/ROM_test/simulation/presynth/@r@o@m_2@k
ROM_test/ROM_test/simulation/presynth/@r@o@m_test
ROM_test/ROM_test/simulation/presynth/testbench
ROM_test/ROM_test/synthesis/synthesis_identify/syntmp
ROM_test/ROM_test/synthesis/synthesis_identify/coreip
ROM_test/ROM_test/synthesis/synthesis_identify/backup
ROM_test/ROM_test/designer/impl1/simulation
ROM_test/ROM_test/smartgen/ROM_2K
ROM_test/ROM_test/viewdraw/vf
ROM_test/ROM_test/viewdraw/sch
ROM_test/ROM_test/viewdraw/sym
ROM_test/ROM_

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