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文件名称:S18_UART_IN_HDL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2015-01-05
  • 文件大小：
    3.4mb
  • 已下载：
    0次
  • 提 供 者：
    flyw*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

带mif文件的，串口模块，verilog编写，经过检验的。-With mif files, serial module, verilog written proven.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

S18_UART_IN_HDL/
S18_UART_IN_HDL/Src/
S18_UART_IN_HDL/Src/div1_8m.v
S18_UART_IN_HDL/Src/filter.v
S18_UART_IN_HDL/Src/rcvr.v
S18_UART_IN_HDL/Src/rcvr_tf.v
S18_UART_IN_HDL/Src/txmit.v
S18_UART_IN_HDL/Src/txmit_tf.v
S18_UART_IN_HDL/Src/uart.v
S18_UART_IN_HDL/Src/uart_if.v
S18_UART_IN_HDL/Src/uart_if_fixed.v
S18_UART_IN_HDL/Src/uart_tb.v
S18_UART_IN_HDL/func_sim/
S18_UART_IN_HDL/func_sim/rcvr.v
S18_UART_IN_HDL/func_sim/transcript
S18_UART_IN_HDL/func_sim/txmit.v
S18_UART_IN_HDL/func_sim/txmit_tf.do
S18_UART_IN_HDL/func_sim/uart.cr.mti
S18_UART_IN_HDL/func_sim/uart.mpf
S18_UART_IN_HDL/func_sim/uart.v
S18_UART_IN_HDL/func_sim/uart_if.v
S18_UART_IN_HDL/func_sim/uart_tb.do
S18_UART_IN_HDL/func_sim/uart_tb.v
S18_UART_IN_HDL/func_sim/uart_tb_fixed.do
S18_UART_IN_HDL/func_sim/vish_stacktrace.vstf
S18_UART_IN_HDL/func_sim/vsim.wlf
S18_UART_IN_HDL/func_sim/wave.do
S18_UART_IN_HDL/func_sim/work/
S18_UART_IN_HDL/func_sim/work/@u@a@r@t_tb/
S18_UART_IN_HDL/func_sim/work/@u@a@r@t_tb/_primary.dat
S18_UART_IN_HDL/func_sim/work/@u@a@r@t_tb/_primary.vhd
S18_UART_IN_HDL/func_sim/work/@u@a@r@t_tb/verilog.asm
S18_UART_IN_HDL/func_sim/work/_info
S18_UART_IN_HDL/func_sim/work/rcvr/
S18_UART_IN_HDL/func_sim/work/rcvr/_primary.dat
S18_UART_IN_HDL/func_sim/work/rcvr/_primary.vhd
S18_UART_IN_HDL/func_sim/work/rcvr/verilog.asm
S18_UART_IN_HDL/func_sim/work/txmit/
S18_UART_IN_HDL/func_sim/work/txmit/_primary.dat
S18_UART_IN_HDL/func_sim/work/txmit/_primary.vhd
S18_UART_IN_HDL/func_sim/work/txmit/verilog.asm
S18_UART_IN_HDL/func_sim/work/uart/
S18_UART_IN_HDL/func_sim/work/uart/_primary.dat
S18_UART_IN_HDL/func_sim/work/uart/_primary.vhd
S18_UART_IN_HDL/func_sim/work/uart/verilog.asm
S18_UART_IN_HDL/func_sim/work/uart_if/
S18_UART_IN_HDL/func_sim/work/uart_if/_primary.dat
S18_UART_IN_HDL/func_sim/work/uart_if/_primary.vhd
S18_UART_IN_HDL/func_sim/work/uart_if/verilog.asm
S18_UART_IN_HDL/pro/
S18_UART_IN_HDL/pro/LED_flush.bsf
S18_UART_IN_HDL/pro/altclklock0.bsf
S18_UART_IN_HDL/pro/altclklock0.v
S18_UART_IN_HDL/pro/altclklock0_bb.v
S18_UART_IN_HDL/pro/async_transmitter.bsf
S18_UART_IN_HDL/pro/cmp_state.ini
S18_UART_IN_HDL/pro/db/
S18_UART_IN_HDL/pro/db/altsyncram_0m31.tdf
S18_UART_IN_HDL/pro/db/altsyncram_8tj.tdf
S18_UART_IN_HDL/pro/db/altsyncram_9un.tdf
S18_UART_IN_HDL/pro/db/altsyncram_eh31.tdf
S18_UART_IN_HDL/pro/db/altsyncram_g5q.tdf
S18_UART_IN_HDL/pro/db/altsyncram_s931.tdf
S18_UART_IN_HDL/pro/db/cntr_cs6.tdf
S18_UART_IN_HDL/pro/db/cntr_gs6.tdf
S18_UART_IN_HDL/pro/db/cntr_ub7.tdf
S18_UART_IN_HDL/pro/db/cntr_vt6.tdf
S18_UART_IN_HDL/pro/db/logic_util_heursitic.dat
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.asm.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.eda.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.fit.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.map.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.sta.qmsg
S18_UART_IN_HDL/pro/db/prev_cmp_uart_if.tan.qmsg
S18_UART_IN_HDL/pro/db/uart_if(0).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(0).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(1).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(1).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(2).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(2).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(3).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(3).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(4).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(4).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(5).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(5).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(6).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(6).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(7).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(7).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(8).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(8).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if(9).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if(9).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(0).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(0).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(1).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(1).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(2).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(2).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(3).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(3).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(4).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(4).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(5).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(5).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(6).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(6).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(7).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(7).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(8).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(8).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.(9).cnf.cdb
S18_UART_IN_HDL/pro/db/uart_if.(9).cnf.hdb
S18_UART_IN_HDL/pro/db/uart_if.ae.hdb
S18_UART_IN_HDL/pro/db/uart_if.asm.qmsg
S18_UART_IN_HDL/pro/db/uart_if.asm.rdb
S18_UART_IN_HDL/pro/db/uart_if.asm_labs.ddb
S18_UART_IN_HDL/pro/db/uart_if.cbx.xml
S18_UART_IN_HDL/pro/db/uart_if.cmp.bpm
S18_UART_IN_HDL/pro/db/uart_if.cmp.cbp
S18_UART_IN_HDL/pro/db/uart_if.cmp.cdb
S18_UART_IN_HDL/pro/db/uart_if.cmp.ecobp
S18_UART_IN_HDL/pro/db/uart_if.cmp.hdb
S18_UART_IN_HDL/pro/db/uart_if.cmp.kpt
S18_UART_IN_HDL/pro/db/uart_if.cmp.logdb
S18_UART_IN_HDL/pro/db/ua

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