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文件名称:eetop.cn_Booth_mutipler_v2

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  • 上传时间:
    2015-01-18
  • 文件大小:
    676.11kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现-The new 32 booth multiplier implementations
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Booth_mutipler/src/tbooth_com.v
Booth_mutipler/src/booth_com.v
Booth_mutipler/src/tbooth_pipeline.v
Booth_mutipler/src/booth_pipeline.v
Booth_mutipler/src
Booth_mutipler/sim/work/_info
Booth_mutipler/sim/work/booth_pipeline/_primary.vhd
Booth_mutipler/sim/work/booth_pipeline/verilog.asm
Booth_mutipler/sim/work/booth_pipeline/_primary.dat
Booth_mutipler/sim/work/booth_pipeline
Booth_mutipler/sim/work/tbooth_pipeline/_primary.vhd
Booth_mutipler/sim/work/tbooth_pipeline/verilog.asm
Booth_mutipler/sim/work/tbooth_pipeline/_primary.dat
Booth_mutipler/sim/work/tbooth_pipeline
Booth_mutipler/sim/work/tbooth_com/_primary.vhd
Booth_mutipler/sim/work/tbooth_com/verilog.asm
Booth_mutipler/sim/work/tbooth_com/_primary.dat
Booth_mutipler/sim/work/tbooth_com
Booth_mutipler/sim/work/booth_com/_primary.vhd
Booth_mutipler/sim/work/booth_com/verilog.asm
Booth_mutipler/sim/work/booth_com/_primary.dat
Booth_mutipler/sim/work/booth_com
Booth_mutipler/sim/work
Booth_mutipler/sim/vsim.wlf
Booth_mutipler/sim/booth_mul.cr.mti
Booth_mutipler/sim/vlog.opt
Booth_mutipler/sim/maxii/_info
Booth_mutipler/sim/maxii/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
Booth_mutipler/sim/maxii/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.asm
Booth_mutipler/sim/maxii/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
Booth_mutipler/sim/maxii/@m@a@x@i@i_@p@r@i@m_@d@f@f@e
Booth_mutipler/sim/maxii/maxii_dffe/_primary.vhd
Booth_mutipler/sim/maxii/maxii_dffe/verilog.asm
Booth_mutipler/sim/maxii/maxii_dffe/_primary.dat
Booth_mutipler/sim/maxii/maxii_dffe
Booth_mutipler/sim/maxii/maxii_latch/_primary.vhd
Booth_mutipler/sim/maxii/maxii_latch/verilog.asm
Booth_mutipler/sim/maxii/maxii_latch/_primary.dat
Booth_mutipler/sim/maxii/maxii_latch
Booth_mutipler/sim/maxii/maxii_mux21/_primary.vhd
Booth_mutipler/sim/maxii/maxii_mux21/verilog.asm
Booth_mutipler/sim/maxii/maxii_mux21/_primary.dat
Booth_mutipler/sim/maxii/maxii_mux21
Booth_mutipler/sim/maxii/maxii_mux41/_primary.vhd
Booth_mutipler/sim/maxii/maxii_mux41/verilog.asm
Booth_mutipler/sim/maxii/maxii_mux41/_primary.dat
Booth_mutipler/sim/maxii/maxii_mux41
Booth_mutipler/sim/maxii/maxii_and1/_primary.vhd
Booth_mutipler/sim/maxii/maxii_and1/verilog.asm
Booth_mutipler/sim/maxii/maxii_and1/_primary.dat
Booth_mutipler/sim/maxii/maxii_and1
Booth_mutipler/sim/maxii/maxii_and16/_primary.vhd
Booth_mutipler/sim/maxii/maxii_and16/verilog.asm
Booth_mutipler/sim/maxii/maxii_and16/_primary.dat
Booth_mutipler/sim/maxii/maxii_and16
Booth_mutipler/sim/maxii/maxii_bmux21/_primary.vhd
Booth_mutipler/sim/maxii/maxii_bmux21/verilog.asm
Booth_mutipler/sim/maxii/maxii_bmux21/_primary.dat
Booth_mutipler/sim/maxii/maxii_bmux21
Booth_mutipler/sim/maxii/maxii_b17mux21/_primary.vhd
Booth_mutipler/sim/maxii/maxii_b17mux21/verilog.asm
Booth_mutipler/sim/maxii/maxii_b17mux21/_primary.dat
Booth_mutipler/sim/maxii/maxii_b17mux21
Booth_mutipler/sim/maxii/maxii_nmux21/_primary.vhd
Booth_mutipler/sim/maxii/maxii_nmux21/verilog.asm
Booth_mutipler/sim/maxii/maxii_nmux21/_primary.dat
Booth_mutipler/sim/maxii/maxii_nmux21
Booth_mutipler/sim/maxii/maxii_b5mux21/_primary.vhd
Booth_mutipler/sim/maxii/maxii_b5mux21/verilog.asm
Booth_mutipler/sim/maxii/maxii_b5mux21/_primary.dat
Booth_mutipler/sim/maxii/maxii_b5mux21
Booth_mutipler/sim/maxii/maxii_asynch_lcell/_primary.vhd
Booth_mutipler/sim/maxii/maxii_asynch_lcell/verilog.asm
Booth_mutipler/sim/maxii/maxii_asynch_lcell/_primary.dat
Booth_mutipler/sim/maxii/maxii_asynch_lcell
Booth_mutipler/sim/maxii/maxii_lcell_register/_primary.vhd
Booth_mutipler/sim/maxii/maxii_lcell_register/verilog.asm
Booth_mutipler/sim/maxii/maxii_lcell_register/_primary.dat
Booth_mutipler/sim/maxii/maxii_lcell_register
Booth_mutipler/sim/maxii/maxii_lcell/_primary.vhd
Booth_mutipler/sim/maxii/maxii_lcell/verilog.asm
Booth_mutipler/sim/maxii/maxii_lcell/_primary.dat
Booth_mutipler/sim/maxii/maxii_lcell
Booth_mutipler/sim/maxii/maxii_ufm/_primary.vhd
Booth_mutipler/sim/maxii/maxii_ufm/verilog.asm
Booth_mutipler/sim/maxii/maxii_ufm/_primary.dat
Booth_mutipler/sim/maxii/maxii_ufm
Booth_mutipler/sim/maxii/maxii_io/_primary.vhd
Booth_mutipler/sim/maxii/maxii_io/verilog.asm
Booth_mutipler/sim/maxii/maxii_io/_primary.dat
Booth_mutipler/sim/maxii/maxii_io
Booth_mutipler/sim/maxii/maxii_routing_wire/_primary.vhd
Booth_mutipler/sim/maxii/maxii_routing_wire/verilog.asm
Booth_mutipler/sim/maxii/maxii_routing_wire/_primary.dat
Booth_mutipler/sim/maxii/maxii_routing_wire
Booth_mutipler/sim/maxii
Booth_mutipler/sim/report_com
Booth_mutipler/sim/modelsim.ini
Booth_mutipler/sim/report_pipeline
Booth_mutipler/sim/vsim_stacktrace.vstf
Booth_mutipler/sim/booth_pipeline_v.sdo
Booth_mutipler/sim/booth_mul.mpf
Booth_mutipler/sim
Booth_mutipler/syn/booth_mul.prj
Booth_mutipler/syn/booth_mul.prd
Booth_mutipler/syn/booth_pipeline.prj
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline_flink.htm
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline_srr.htm
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline_toc.htm
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline.plg
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline_cons_ui.tcl
Booth_mutipler/syn/rev_2/syntmp/booth_pipeline.msg
Booth_mutipler/syn/rev_2/syntmp
Boot

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