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文件名称:plj

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Windows] [程序]
  • 上传时间：
    2015-01-25
  • 文件大小：
    799.39kb
  • 已下载：
    0次
  • 提 供 者：
    范***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

时钟分频器原理与实现，计数跳变的频率和加减模式可实时变化，通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nano experiments. Counting frequency, subtraction selection and initialization by a toggle switch panel and Reset buttons to achieve.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

plj/b2a.Vhd
plj/b2a_plj.SchLib
plj/banshangtu.SchDoc
plj/control_plj.SchLib
plj/dinlatch_plj.SchLib
plj/FPGA_Project1.PrjFpg
plj/FPGA_Project1.SO
plj/FPGA_Project2.PrjFpg
plj/FPGA_Project2.SO
plj/FPGA_Project3.PrjFpg
plj/FPGA_Project3.SO
plj/FPGA_Project4.PrjFpg
plj/FPGA_Project4.PrjFpgStructure
plj/FPGA_Project4.SO
plj/FPGA_Project5.PrjFpg
plj/FPGA_Project6.PrjFpg
plj/FPGA_Project6.PrjFpgStructure
plj/History/banshangtu.~(1).SchDoc.Zip
plj/History/FPGA_Project1.~(1).PrjFpg.Zip
plj/History/FPGA_Project1.~(2).PrjFpg.Zip
plj/History/FPGA_Project2.~(1).PrjFpg.Zip
plj/History/FPGA_Project2.~(1).SO.Zip
plj/History/FPGA_Project2.~(10).PrjFpg.Zip
plj/History/FPGA_Project2.~(11).PrjFpg.Zip
plj/History/FPGA_Project2.~(12).PrjFpg.Zip
plj/History/FPGA_Project2.~(2).PrjFpg.Zip
plj/History/FPGA_Project2.~(2).SO.Zip
plj/History/FPGA_Project2.~(3).PrjFpg.Zip
plj/History/FPGA_Project2.~(4).PrjFpg.Zip
plj/History/FPGA_Project2.~(5).PrjFpg.Zip
plj/History/FPGA_Project2.~(6).PrjFpg.Zip
plj/History/FPGA_Project2.~(7).PrjFpg.Zip
plj/History/FPGA_Project2.~(8).PrjFpg.Zip
plj/History/FPGA_Project2.~(9).PrjFpg.Zip
plj/History/FPGA_Project3.~(1).PrjFpg.Zip
plj/History/FPGA_Project3.~(2).PrjFpg.Zip
plj/History/FPGA_Project4.~(1).PrjFpg.Zip
plj/History/FPGA_Project4.~(2).PrjFpg.Zip
plj/History/FPGA_Project4.~(3).PrjFpg.Zip
plj/History/FPGA_Project4.~(4).PrjFpg.Zip
plj/History/FPGA_Project5.~(1).PrjFpg.Zip
plj/History/FPGA_Project5.~(2).PrjFpg.Zip
plj/History/FPGA_Project6.~(1).PrjFpg.Zip
plj/History/pinlvji.~(1).PrjFpg.Zip
plj/History/pinlvji.~(2).PrjFpg.Zip
plj/History/ProjectOutputs/Sheet2.~(1).VHD.Zip
plj/History/ProjectOutputs/Sheet3.~(1).VHD.Zip
plj/History/ProjectOutputs/Sheet3.~(2).VHD.Zip
plj/History/ProjectOutputs/Sheet3.~(3).VHD.Zip
plj/History/Sheet1.~(1).SchDoc.Zip
plj/History/Sheet1.~(2).SchDoc.Zip
plj/History/Sheet1.~(3).SchDoc.Zip
plj/History/Sheet1.~(4).SchDoc.Zip
plj/History/Sheet1.~(5).SchDoc.Zip
plj/History/Sheet1.~(6).SchDoc.Zip
plj/History/Sheet2.~(1).SchDoc.Zip
plj/History/Sheet2.~(2).SchDoc.Zip
plj/History/Sheet2.~(3).SchDoc.Zip
plj/History/Sheet3.~(1).SchDoc.Zip
plj/History/Sheet3.~(2).SchDoc.Zip
plj/History/Sheet3.~(3).SchDoc.Zip
plj/History/Test_cnt10.~(1).VHDTST.Zip
plj/History/Test_cnt10.~(10).VHDTST.Zip
plj/History/Test_cnt10.~(11).VHDTST.Zip
plj/History/Test_cnt10.~(2).VHDTST.Zip
plj/History/Test_cnt10.~(3).VHDTST.Zip
plj/History/Test_cnt10.~(4).VHDTST.Zip
plj/History/Test_cnt10.~(5).VHDTST.Zip
plj/History/Test_cnt10.~(6).VHDTST.Zip
plj/History/Test_cnt10.~(7).VHDTST.Zip
plj/History/Test_cnt10.~(8).VHDTST.Zip
plj/History/Test_cnt10.~(9).VHDTST.Zip
plj/History/Test_fpga_project4.~(1).VHDTST.Zip
plj/History/VHDL2.~(1).Vhd.Zip
plj/History/VHDL2.~(2).Vhd.Zip
plj/History/VHDL2.~(3).Vhd.Zip
plj/History/VHDL2.~(4).Vhd.Zip
plj/History/VHDL3.~(1).Vhd.Zip
plj/History/VHDL3.~(2).Vhd.Zip
plj/History/VHDL4.~(1).Vhd.Zip
plj/History/VHDL4.~(2).Vhd.Zip
plj/History/VHDL4.~(3).Vhd.Zip
plj/jishuqi_plj.SchLib
plj/lcd_scan_plj.SchLib
plj/pinlvji.PrjFpg
plj/pinlvji.PrjFpgStructure
plj/Project Logs for FPGA_Project4/Sheet1 SCH ECO 2013-5-22 19-51-04.LOG
plj/Project Logs for pinlvji/banshangtu SCH ECO 2013-5-26 20-47-55.LOG
plj/Project Logs for pinlvji/Sheet1 SCH ECO 2013-5-26 20-32-24.LOG
plj/Project Logs for pinlvji/Sheet1 SCH ECO 2013-5-26 20-46-06.LOG
plj/ProjectOutputs/banshangtu.VHD
plj/ProjectOutputs/FPGA_Project1_BUILT_IN_ALDEC/FPGA_Project1.top
plj/ProjectOutputs/FPGA_Project2_BUILT_IN_ALDEC/FPGA_Project2.top
plj/ProjectOutputs/FPGA_Project3_BUILT_IN_ALDEC/FPGA_Project3.top
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4/0FPGA_Project4.mgf
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4/1FPGA_Project4.mgf
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4/3FPGA_Project4.mgf
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4/elaboration.log
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4/FPGA_Project4.lib
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/FPGA_Project4.top
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/library.cfg
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/projlib.cfg
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/results.txt
plj/ProjectOutputs/FPGA_Project4_BUILT_IN_ALDEC/wave.asdb
plj/ProjectOutputs/Sheet1.VHD
plj/ProjectOutputs/Sheet2.VHD
plj/ProjectOutputs/Sheet3.VHD
plj/ProjectOutputs/__Previews/banshangtu.VHDPreview
plj/ProjectOutputs/__Previews/Sheet1.VHDPreview
plj/ProjectOutputs/__Previews/Sheet2.VHDPreview
plj/ProjectOutputs/__Previews/Sheet3.VHDPreview
plj/Sheet3.SchDoc
plj/Test_cnt10.VHDTST
plj/Test_controlor.VHDTST
plj/Test_dlatch.VHDTST
plj/Test_fpga_project4.VHDTST
plj/VHDL1.Vhd
plj/VHDL2.Vhd
plj/VHDL3.Vhd
plj/VHDL4.Vhd
plj/__Previews/b2a.VhdPreview
plj/__Previews/banshangtu.SchDocPreview
plj/__Previews/Sheet1.SchDocPreview
plj/__Previews/Sheet2.SchDocPreview
plj/__Previews/Sheet3.SchDocPreview
plj/__Previews/Test_cnt10.VHDTSTPreview
plj/__Previews/Test_controlor.VHDTSTPreview
plj/__Previews/Test_dlatch.VHDTSTPreview
plj/__Previews/Test_fpga_project4.VHDTSTPreview
plj/__Previews/VHDL1.VhdPreview
plj/__Previews/VHDL2.VhdPreview
plj/__Previe

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