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文件名称:Example-b8-1

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2015-03-08
  • 文件大小：
    3.91mb
  • 已下载：
    0次
  • 提 供 者：
    朱****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用ModelSim对Altera设计进行功能仿真的简要操作步骤　　1.建立仿真工程

2.Altera仿真库的编译与映射

3.编译HDL源代码和Testbench

4.启动仿真器并加载设计顶层

5.打开观测窗口，添加信号

6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project

Compilation and mapping 2.Altera emulation library

3. Compile HDL source code and Testbench

4. Start the emulator and the top load design

5. Open the observation window, add signals

6. execution simulation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-b8-1/Altera_lib_files/220model.txt
Example-b8-1/Altera_lib_files/220model.v
Example-b8-1/Altera_lib_files/220model.vhd
Example-b8-1/Altera_lib_files/220model_87.vhd
Example-b8-1/Altera_lib_files/220pack.vhd
Example-b8-1/Altera_lib_files/altera_mf.txt
Example-b8-1/Altera_lib_files/altera_mf.v
Example-b8-1/Altera_lib_files/altera_mf.vhd
Example-b8-1/Altera_lib_files/altera_mf_87.vhd
Example-b8-1/Altera_lib_files/altera_mf_components.vhd
Example-b8-1/Altera_lib_files/stratix_atoms.v
Example-b8-1/Altera_lib_files/stratix_atoms.vhd
Example-b8-1/Altera_lib_files/stratix_components.vhd
Example-b8-1/func_sim/dpram8x32.v
Example-b8-1/func_sim/func_sim.cr.mti
Example-b8-1/func_sim/func_sim.mpf
Example-b8-1/func_sim/func_sim_wave.wlf
Example-b8-1/func_sim/pllx2.v
Example-b8-1/func_sim/pll_ram.v
Example-b8-1/func_sim/pll_ram_tb.v
Example-b8-1/func_sim/transcript
Example-b8-1/func_sim/vsim.wlf
Example-b8-1/func_sim/wave.bmp
Example-b8-1/func_sim/wave.do
Example-b8-1/func_sim/work/dpram8x32/verilog.asm
Example-b8-1/func_sim/work/dpram8x32/_primary.dat
Example-b8-1/func_sim/work/dpram8x32/_primary.vhd
Example-b8-1/func_sim/work/pllx2/verilog.asm
Example-b8-1/func_sim/work/pllx2/_primary.dat
Example-b8-1/func_sim/work/pllx2/_primary.vhd
Example-b8-1/func_sim/work/pll_ram/verilog.asm
Example-b8-1/func_sim/work/pll_ram/_primary.dat
Example-b8-1/func_sim/work/pll_ram/_primary.vhd
Example-b8-1/func_sim/work/pll_ram_tb/verilog.asm
Example-b8-1/func_sim/work/pll_ram_tb/_primary.dat
Example-b8-1/func_sim/work/pll_ram_tb/_primary.vhd
Example-b8-1/func_sim/work/_info
Example-b8-1/pll_ram/cmp_state.ini
Example-b8-1/pll_ram/db/altsyncram_06q1.tdf
Example-b8-1/pll_ram/db/altsyncram_7bc1.tdf
Example-b8-1/pll_ram/db/altsyncram_bvp1.tdf
Example-b8-1/pll_ram/db/pll_ram(0).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(0).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram(1).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(1).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram(2).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(2).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram(3).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(3).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram(4).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(4).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram(5).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram(5).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(0).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(0).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(1).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(1).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(2).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(2).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(3).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(3).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(4).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(4).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.(5).cnf.cdb
Example-b8-1/pll_ram/db/pll_ram.(5).cnf.hdb
Example-b8-1/pll_ram/db/pll_ram.asm.qmsg
Example-b8-1/pll_ram/db/pll_ram.asm_labs.ddb
Example-b8-1/pll_ram/db/pll_ram.cbx.xml
Example-b8-1/pll_ram/db/pll_ram.cmp.cdb
Example-b8-1/pll_ram/db/pll_ram.cmp.hdb
Example-b8-1/pll_ram/db/pll_ram.cmp.logdb
Example-b8-1/pll_ram/db/pll_ram.cmp.rdb
Example-b8-1/pll_ram/db/pll_ram.cmp.tdb
Example-b8-1/pll_ram/db/pll_ram.cmp0.ddb
Example-b8-1/pll_ram/db/pll_ram.cmp2.ddb
Example-b8-1/pll_ram/db/pll_ram.dbp
Example-b8-1/pll_ram/db/pll_ram.db_info
Example-b8-1/pll_ram/db/pll_ram.eco.cdb
Example-b8-1/pll_ram/db/pll_ram.eda.qmsg
Example-b8-1/pll_ram/db/pll_ram.fit.qmsg
Example-b8-1/pll_ram/db/pll_ram.hier_info
Example-b8-1/pll_ram/db/pll_ram.hif
Example-b8-1/pll_ram/db/pll_ram.map.cdb
Example-b8-1/pll_ram/db/pll_ram.map.hdb
Example-b8-1/pll_ram/db/pll_ram.map.logdb
Example-b8-1/pll_ram/db/pll_ram.map.qmsg
Example-b8-1/pll_ram/db/pll_ram.pre_map.cdb
Example-b8-1/pll_ram/db/pll_ram.pre_map.hdb
Example-b8-1/pll_ram/db/pll_ram.psp
Example-b8-1/pll_ram/db/pll_ram.pss
Example-b8-1/pll_ram/db/pll_ram.rpp.qmsg
Example-b8-1/pll_ram/db/pll_ram.rtlv.hdb
Example-b8-1/pll_ram/db/pll_ram.rtlv_sg.cdb
Example-b8-1/pll_ram/db/pll_ram.rtlv_sg_swap.cdb
Example-b8-1/pll_ram/db/pll_ram.sgate.rvd
Example-b8-1/pll_ram/db/pll_ram.sgate_sm.rvd
Example-b8-1/pll_ram/db/pll_ram.sgdiff.cdb
Example-b8-1/pll_ram/db/pll_ram.sgdiff.hdb
Example-b8-1/pll_ram/db/pll_ram.signalprobe.cdb
Example-b8-1/pll_ram/db/pll_ram.sld_design_entry.sci
Example-b8-1/pll_ram/db/pll_ram.sld_design_entry_dsc.sci
Example-b8-1/pll_ram/db/pll_ram.syn_hier_info
Example-b8-1/pll_ram/db/pll_ram.tan.qmsg
Example-b8-1/pll_ram/db/pll_ram.tis_db_list.ddb
Example-b8-1/pll_ram/db/pll_ram_cmp.qrpt
Example-b8-1/pll_ram/db/pll_ram_hier_info
Example-b8-1/pll_ram/db/pll_ram_syn_hier_info
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.asm.qmsg
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.eda.qmsg
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.fit.qmsg
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.map.qmsg
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.qmsg
Example-b8-1/pll_ram/db/prev_cmp_pll_ram.tan.qmsg
Example-b8-1/pll_ram/dpram8x32.v
Example-b8-1/pll_ram/pllx2.v
Example-b8-1/pll_ram/pll_ram.asm.rpt
Example-b8-1/pll_ram/pll_ram.done
Example-b8-1/pll_ram/pll_ram.eda.rpt
Example-b8-1/pll_ram/pll_ram.fit.eqn
Example-b8-1/pll_ram/pll_ram.fit.rpt
Example-b8-1/

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