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文件名称:Example-b8-2

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2015-03-08
  • 文件大小：
    2.81mb
  • 已下载：
    0次
  • 提 供 者：
    朱****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用ModelSim对Altera设计进行时序仿真的简要操作步骤　　1.建立工程，设置仿真工具选项参数

2.使用Quartus II编译工程

3.建立仿真工程

4.Altera仿真库的编译与映射

5.编译HDL源代码和Testbench

6.启动仿真器并加载设计顶层

7.打开观测窗口，添加信号

8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish project simulation tool options set parameters

2. Use the Quartus II compilation project

3. Establish simulation project

Compilation and mapping 4.Altera emulation library

5. Compile HDL source code and Testbench

6. Start the emulator and the top load design

7. Open the observation window, add signals

8. perform simulation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-b8-2/Altera_lib_files/220model.txt
Example-b8-2/Altera_lib_files/220model.v
Example-b8-2/Altera_lib_files/220model.vhd
Example-b8-2/Altera_lib_files/220model_87.vhd
Example-b8-2/Altera_lib_files/220pack.vhd
Example-b8-2/Altera_lib_files/altera_mf.txt
Example-b8-2/Altera_lib_files/altera_mf.v
Example-b8-2/Altera_lib_files/altera_mf.vhd
Example-b8-2/Altera_lib_files/altera_mf_87.vhd
Example-b8-2/Altera_lib_files/altera_mf_components.vhd
Example-b8-2/Altera_lib_files/stratix_atoms.v
Example-b8-2/Altera_lib_files/stratix_atoms.vhd
Example-b8-2/Altera_lib_files/stratix_components.vhd
Example-b8-2/func_sim/dpram8x32.v
Example-b8-2/func_sim/func_sim.cr.mti
Example-b8-2/func_sim/func_sim.mpf
Example-b8-2/func_sim/func_sim_wave.wlf
Example-b8-2/func_sim/pllx2.v
Example-b8-2/func_sim/pll_ram.v
Example-b8-2/func_sim/pll_ram_tb.v
Example-b8-2/func_sim/transcript
Example-b8-2/func_sim/vsim.wlf
Example-b8-2/func_sim/wave.bmp
Example-b8-2/func_sim/wave.do
Example-b8-2/func_sim/work/dpram8x32/verilog.asm
Example-b8-2/func_sim/work/dpram8x32/_primary.dat
Example-b8-2/func_sim/work/dpram8x32/_primary.vhd
Example-b8-2/func_sim/work/pllx2/verilog.asm
Example-b8-2/func_sim/work/pllx2/_primary.dat
Example-b8-2/func_sim/work/pllx2/_primary.vhd
Example-b8-2/func_sim/work/pll_ram/verilog.asm
Example-b8-2/func_sim/work/pll_ram/_primary.dat
Example-b8-2/func_sim/work/pll_ram/_primary.vhd
Example-b8-2/func_sim/work/pll_ram_tb/verilog.asm
Example-b8-2/func_sim/work/pll_ram_tb/_primary.dat
Example-b8-2/func_sim/work/pll_ram_tb/_primary.vhd
Example-b8-2/func_sim/work/_info
Example-b8-2/pll_ram/cmp_state.ini
Example-b8-2/pll_ram/db/altsyncram_7bc1.tdf
Example-b8-2/pll_ram/db/pll_ram(0).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(0).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(1).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(1).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(2).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(2).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(3).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(3).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(4).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(4).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(5).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(5).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(6).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(6).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram(7).cnf.cdb
Example-b8-2/pll_ram/db/pll_ram(7).cnf.hdb
Example-b8-2/pll_ram/db/pll_ram.db_info
Example-b8-2/pll_ram/db/pll_ram.eco.cdb
Example-b8-2/pll_ram/db/pll_ram.sld_design_entry.sci
Example-b8-2/pll_ram/db/pll_ram_cmp.qrpt
Example-b8-2/pll_ram/db/pll_ram_hier_info
Example-b8-2/pll_ram/db/pll_ram_syn_hier_info
Example-b8-2/pll_ram/dpram8x32.v
Example-b8-2/pll_ram/pllx2.v
Example-b8-2/pll_ram/pll_ram.asm.rpt
Example-b8-2/pll_ram/pll_ram.done
Example-b8-2/pll_ram/pll_ram.eda.rpt
Example-b8-2/pll_ram/pll_ram.fit.eqn
Example-b8-2/pll_ram/pll_ram.fit.rpt
Example-b8-2/pll_ram/pll_ram.flow.rpt
Example-b8-2/pll_ram/pll_ram.map.eqn
Example-b8-2/pll_ram/pll_ram.map.rpt
Example-b8-2/pll_ram/pll_ram.pin
Example-b8-2/pll_ram/pll_ram.pof
Example-b8-2/pll_ram/pll_ram.qpf
Example-b8-2/pll_ram/pll_ram.qsf
Example-b8-2/pll_ram/pll_ram.qws
Example-b8-2/pll_ram/pll_ram.sof
Example-b8-2/pll_ram/pll_ram.tan.rpt
Example-b8-2/pll_ram/pll_ram.tan.summary
Example-b8-2/pll_ram/pll_ram.v
Example-b8-2/pll_ram/pll_ram_assignment_defaults.qdf
Example-b8-2/pll_ram/simulation/modelsim/pll_ram.vo
Example-b8-2/pll_ram/simulation/modelsim/pll_ram_modelsim.xrf
Example-b8-2/pll_ram/simulation/modelsim/pll_ram_v.sdo
Example-b8-2/source/dpram8x32.v
Example-b8-2/source/dpram8x32_bb.v
Example-b8-2/source/dpram8x32_wave0.jpg
Example-b8-2/source/dpram8x32_wave1.jpg
Example-b8-2/source/dpram8x32_wave2.jpg
Example-b8-2/source/dpram8x32_wave3.jpg
Example-b8-2/source/dpram8x32_waveforms.html
Example-b8-2/source/pllx2.v
Example-b8-2/source/pllx2_bb.v
Example-b8-2/source/pll_ram.v
Example-b8-2/source/pll_ram_tb.v
Example-b8-2/source/post-simulation/modelsim/pll_ram.vo
Example-b8-2/source/post-simulation/modelsim/pll_ram_modelsim.xrf
Example-b8-2/source/post-simulation/modelsim/pll_ram_v.sdo
Example-b8-2/timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
Example-b8-2/timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
Example-b8-2/timing_sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
Example-b8-2/timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
Example-b8-2/timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
Example-b8-2/timing_sim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
Example-b8-2/timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
Example-b8-2/timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
Example-b8-2/timing_sim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
Example-b8-2/timing_sim/work/@m@f_pll_reg/verilog.asm
Example-b8-2/timing_sim/work/@m@f_pll_reg/_primary.dat
Example-b8-2/timing_sim/work/@m@f_pll_reg/_primary.vhd
Example-b8-2/timing_sim/work/@m@f_ram7x20_syn/verilog.asm
Example-b8-2/timing_sim/work/@m@f_ram7x20_syn/_primary.dat
Example-b8-2/timing_sim/work/@m@f_ram7x20_syn/_

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