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文件名称:Project6(finish)

  • 所属分类：
    OS Develop
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-03-12
  • 文件大小：
    133.09kb
  • 已下载：
    0次
  • 提 供 者：
    zhql*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

modelsim下仿真通过，用Verilog写的多周期CPU，是计算机组成原理的大作业，供学弟学妹参考。-Under modelsim simulation by using Verilog write multi-cycle CPU, is composed of a large computer operating principle for mentees reference.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Project6(finish)/alu.v
Project6(finish)/be_load.v
Project6(finish)/be_save.v
Project6(finish)/code.txt
Project6(finish)/controller.v
Project6(finish)/controller.v.bak
Project6(finish)/dm.v
Project6(finish)/ext.v
Project6(finish)/gpr.v
Project6(finish)/head_mips.v
Project6(finish)/im.v
Project6(finish)/mips.cr.mti
Project6(finish)/mips.mpf
Project6(finish)/mips.v
Project6(finish)/mux.v
Project6(finish)/npc.v
Project6(finish)/pc.v
Project6(finish)/testbench.v
Project6(finish)/vsim.wlf
Project6(finish)/wave1.bmp
Project6(finish)/wave2.bmp
Project6(finish)/work/alu/verilog.asm64
Project6(finish)/work/alu/verilog.rw64
Project6(finish)/work/alu/_primary.dat
Project6(finish)/work/alu/_primary.dbs
Project6(finish)/work/alu/_primary.vhd
Project6(finish)/work/be_load/verilog.asm64
Project6(finish)/work/be_load/verilog.rw64
Project6(finish)/work/be_load/_primary.dat
Project6(finish)/work/be_load/_primary.dbs
Project6(finish)/work/be_load/_primary.vhd
Project6(finish)/work/be_save/verilog.asm64
Project6(finish)/work/be_save/verilog.rw64
Project6(finish)/work/be_save/_primary.dat
Project6(finish)/work/be_save/_primary.dbs
Project6(finish)/work/be_save/_primary.vhd
Project6(finish)/work/controller/verilog.asm64
Project6(finish)/work/controller/verilog.rw64
Project6(finish)/work/controller/_primary.dat
Project6(finish)/work/controller/_primary.dbs
Project6(finish)/work/controller/_primary.vhd
Project6(finish)/work/dm/verilog.asm64
Project6(finish)/work/dm/verilog.rw64
Project6(finish)/work/dm/_primary.dat
Project6(finish)/work/dm/_primary.dbs
Project6(finish)/work/dm/_primary.vhd
Project6(finish)/work/gpr/verilog.asm64
Project6(finish)/work/gpr/verilog.rw64
Project6(finish)/work/gpr/_primary.dat
Project6(finish)/work/gpr/_primary.dbs
Project6(finish)/work/gpr/_primary.vhd
Project6(finish)/work/im/verilog.asm64
Project6(finish)/work/im/verilog.rw64
Project6(finish)/work/im/_primary.dat
Project6(finish)/work/im/_primary.dbs
Project6(finish)/work/im/_primary.vhd
Project6(finish)/work/mips/verilog.asm64
Project6(finish)/work/mips/verilog.rw64
Project6(finish)/work/mips/_primary.dat
Project6(finish)/work/mips/_primary.dbs
Project6(finish)/work/mips/_primary.vhd
Project6(finish)/work/mux32/verilog.asm64
Project6(finish)/work/mux32/verilog.rw64
Project6(finish)/work/mux32/_primary.dat
Project6(finish)/work/mux32/_primary.dbs
Project6(finish)/work/mux32/_primary.vhd
Project6(finish)/work/mux5/verilog.asm64
Project6(finish)/work/mux5/verilog.rw64
Project6(finish)/work/mux5/_primary.dat
Project6(finish)/work/mux5/_primary.dbs
Project6(finish)/work/mux5/_primary.vhd
Project6(finish)/work/npc/verilog.asm64
Project6(finish)/work/npc/verilog.rw64
Project6(finish)/work/npc/_primary.dat
Project6(finish)/work/npc/_primary.dbs
Project6(finish)/work/npc/_primary.vhd
Project6(finish)/work/pc/verilog.asm64
Project6(finish)/work/pc/verilog.rw64
Project6(finish)/work/pc/_primary.dat
Project6(finish)/work/pc/_primary.dbs
Project6(finish)/work/pc/_primary.vhd
Project6(finish)/work/sign_ext/verilog.asm64
Project6(finish)/work/sign_ext/verilog.rw64
Project6(finish)/work/sign_ext/_primary.dat
Project6(finish)/work/sign_ext/_primary.dbs
Project6(finish)/work/sign_ext/_primary.vhd
Project6(finish)/work/testbench_mips/verilog.asm64
Project6(finish)/work/testbench_mips/verilog.rw64
Project6(finish)/work/testbench_mips/_primary.dat
Project6(finish)/work/testbench_mips/_primary.dbs
Project6(finish)/work/testbench_mips/_primary.vhd
Project6(finish)/work/zero_ext/verilog.asm64
Project6(finish)/work/zero_ext/verilog.rw64
Project6(finish)/work/zero_ext/_primary.dat
Project6(finish)/work/zero_ext/_primary.dbs
Project6(finish)/work/zero_ext/_primary.vhd
Project6(finish)/work/_info
Project6(finish)/work/_vmake
Project6(finish)/work/alu
Project6(finish)/work/be_load
Project6(finish)/work/be_save
Project6(finish)/work/controller
Project6(finish)/work/dm
Project6(finish)/work/gpr
Project6(finish)/work/im
Project6(finish)/work/mips
Project6(finish)/work/mux32
Project6(finish)/work/mux5
Project6(finish)/work/npc
Project6(finish)/work/pc
Project6(finish)/work/sign_ext
Project6(finish)/work/testbench_mips
Project6(finish)/work/zero_ext
Project6(finish)/work/_temp
Project6(finish)/work
Project6(finish)

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