文件名称:async_fifo_prj
-
所属分类：
- 标签属性：
- 上传时间：2015-03-15
-
文件大小：26.54mb
-
已下载：0次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code. I believe you will like it.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
async_fifo_prj/
async_fifo_prj/doc/
async_fifo_prj/doc/异步FIFO设计.doc
async_fifo_prj/imp/
async_fifo_prj/imp/Top_MyFIFO_Ctrl.asm.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.done
async_fifo_prj/imp/Top_MyFIFO_Ctrl.eda.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.smsg
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl.flow.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.jdi
async_fifo_prj/imp/Top_MyFIFO_Ctrl.map.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.map.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl.pin
async_fifo_prj/imp/Top_MyFIFO_Ctrl.qpf
async_fifo_prj/imp/Top_MyFIFO_Ctrl.qsf
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sof
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sta.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sta.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl_assignment_defaults.qdf
async_fifo_prj/imp/blk_mem_gen_v2_7.qip
async_fifo_prj/imp/blk_mem_gen_v2_7.v
async_fifo_prj/imp/blk_mem_gen_v2_7_bb.v
async_fifo_prj/imp/blk_mem_gen_v2_7_inst.v
async_fifo_prj/imp/db/
async_fifo_prj/imp/db/Top_MyFIFO_Ctrl.db_info
async_fifo_prj/imp/db/Top_MyFIFO_Ctrl.sld_design_entry.sci
async_fifo_prj/imp/db/altsyncram_kkj1.tdf
async_fifo_prj/imp/db/logic_util_heursitic.dat
async_fifo_prj/imp/db/prev_cmp_Top_MyFIFO_Ctrl.qmsg
async_fifo_prj/imp/greybox_tmp/
async_fifo_prj/imp/greybox_tmp/cbx_args.txt
async_fifo_prj/imp/incremental_db/
async_fifo_prj/imp/incremental_db/README
async_fifo_prj/imp/incremental_db/compiled_partitions/
async_fifo_prj/imp/incremental_db/compiled_partitions/Top_MyFIFO_Ctrl.db_info
async_fifo_prj/imp/simulation/
async_fifo_prj/imp/simulation/modelsim/
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl.sft
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_0c_slow.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_0c_vhd_slow.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_85c_slow.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_85c_vhd_slow.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_min_1200mv_0c_fast.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_min_1200mv_0c_vhd_fast.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_modelsim.xrf
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_vhd.sdo
async_fifo_prj/sim/
async_fifo_prj/sim/tb_Top_MyFIFO_Ctrl.cr.mti
async_fifo_prj/sim/tb_Top_MyFIFO_Ctrl.mpf
async_fifo_prj/sim/vsim.wlf
async_fifo_prj/sim/work/
async_fifo_prj/sim/work/@gray2@norm/
async_fifo_prj/sim/work/@gray2@norm/_primary.dat
async_fifo_prj/sim/work/@gray2@norm/_primary.dbs
async_fifo_prj/sim/work/@gray2@norm/_primary.vhd
async_fifo_prj/sim/work/@gray2@norm/verilog.prw
async_fifo_prj/sim/work/@gray2@norm/verilog.psm
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.dat
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.dbs
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.vhd
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/verilog.prw
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/verilog.psm
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.dat
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.dbs
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.vhd
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/verilog.prw
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/verilog.psm
async_fifo_prj/sim/work/@norm2@gray/
async_fifo_prj/sim/work/@norm2@gray/_primary.dat
async_fifo_prj/sim/work/@norm2@gray/_primary.dbs
async_fifo_prj/sim/work/@norm2@gray/_primary.vhd
async_fifo_prj/sim/work/@norm2@gray/verilog.prw
async_fifo_prj/sim/work/@norm2@gray/verilog.psm
async_fifo_prj/sim/work/@prbs@any@checker/
async_fifo_prj/sim/work/@prbs@any@checker/_primary.dat
async_fifo_prj/sim/work/@prbs@any@checker/_primary.dbs
async_fifo_prj/sim/work/@prbs@any@checker/_primary.vhd
async_fifo_prj/sim/work/@prbs@any@checker/verilog.prw
async_fifo_prj/sim/work/@prbs@any@checker/verilog.psm
async_fifo_prj/sim/work/@prbs@any@generator/
async_fifo_prj/sim/work/@prbs@any@generator/_primary.dat
async_fifo_prj/sim/work/@prbs@any@generator/_primary.dbs
async_fifo_prj/sim/work/@prbs@any@generator/_primary.vhd
async_fifo_prj/sim/work/@prbs@any@generator/verilog.prw
async_fifo_prj/sim/work/@prbs@any@generator/verilog.psm
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.dat
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.dbs
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.vhd
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/verilog.prw
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/verilog.psm
async_fifo_prj/sim/work/_info
async_fifo_prj/sim/work/_temp/
async_fifo_prj/sim/work/_vmake
async_fifo_prj/sim/work/blk_mem_gen_v2_7/
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.dat
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.dbs
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.vhd
async_fifo_prj/sim/work/blk_mem_gen_v2_7/verilog.prw
async_fifo_prj/sim/work/blk_mem_gen_v2_7/verilog.psm
async_fifo_prj/sim/work/tb_@top_@my@f@i@
async_fifo_prj/doc/
async_fifo_prj/doc/异步FIFO设计.doc
async_fifo_prj/imp/
async_fifo_prj/imp/Top_MyFIFO_Ctrl.asm.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.done
async_fifo_prj/imp/Top_MyFIFO_Ctrl.eda.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.smsg
async_fifo_prj/imp/Top_MyFIFO_Ctrl.fit.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl.flow.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.jdi
async_fifo_prj/imp/Top_MyFIFO_Ctrl.map.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.map.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl.pin
async_fifo_prj/imp/Top_MyFIFO_Ctrl.qpf
async_fifo_prj/imp/Top_MyFIFO_Ctrl.qsf
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sof
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sta.rpt
async_fifo_prj/imp/Top_MyFIFO_Ctrl.sta.summary
async_fifo_prj/imp/Top_MyFIFO_Ctrl_assignment_defaults.qdf
async_fifo_prj/imp/blk_mem_gen_v2_7.qip
async_fifo_prj/imp/blk_mem_gen_v2_7.v
async_fifo_prj/imp/blk_mem_gen_v2_7_bb.v
async_fifo_prj/imp/blk_mem_gen_v2_7_inst.v
async_fifo_prj/imp/db/
async_fifo_prj/imp/db/Top_MyFIFO_Ctrl.db_info
async_fifo_prj/imp/db/Top_MyFIFO_Ctrl.sld_design_entry.sci
async_fifo_prj/imp/db/altsyncram_kkj1.tdf
async_fifo_prj/imp/db/logic_util_heursitic.dat
async_fifo_prj/imp/db/prev_cmp_Top_MyFIFO_Ctrl.qmsg
async_fifo_prj/imp/greybox_tmp/
async_fifo_prj/imp/greybox_tmp/cbx_args.txt
async_fifo_prj/imp/incremental_db/
async_fifo_prj/imp/incremental_db/README
async_fifo_prj/imp/incremental_db/compiled_partitions/
async_fifo_prj/imp/incremental_db/compiled_partitions/Top_MyFIFO_Ctrl.db_info
async_fifo_prj/imp/simulation/
async_fifo_prj/imp/simulation/modelsim/
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl.sft
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_0c_slow.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_0c_vhd_slow.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_85c_slow.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_8_1200mv_85c_vhd_slow.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_min_1200mv_0c_fast.vho
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_min_1200mv_0c_vhd_fast.sdo
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_modelsim.xrf
async_fifo_prj/imp/simulation/modelsim/Top_MyFIFO_Ctrl_vhd.sdo
async_fifo_prj/sim/
async_fifo_prj/sim/tb_Top_MyFIFO_Ctrl.cr.mti
async_fifo_prj/sim/tb_Top_MyFIFO_Ctrl.mpf
async_fifo_prj/sim/vsim.wlf
async_fifo_prj/sim/work/
async_fifo_prj/sim/work/@gray2@norm/
async_fifo_prj/sim/work/@gray2@norm/_primary.dat
async_fifo_prj/sim/work/@gray2@norm/_primary.dbs
async_fifo_prj/sim/work/@gray2@norm/_primary.vhd
async_fifo_prj/sim/work/@gray2@norm/verilog.prw
async_fifo_prj/sim/work/@gray2@norm/verilog.psm
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.dat
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.dbs
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/_primary.vhd
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/verilog.prw
async_fifo_prj/sim/work/@my@f@i@f@o1024x8/verilog.psm
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.dat
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.dbs
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/_primary.vhd
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/verilog.prw
async_fifo_prj/sim/work/@my@f@i@f@o_@ctrl/verilog.psm
async_fifo_prj/sim/work/@norm2@gray/
async_fifo_prj/sim/work/@norm2@gray/_primary.dat
async_fifo_prj/sim/work/@norm2@gray/_primary.dbs
async_fifo_prj/sim/work/@norm2@gray/_primary.vhd
async_fifo_prj/sim/work/@norm2@gray/verilog.prw
async_fifo_prj/sim/work/@norm2@gray/verilog.psm
async_fifo_prj/sim/work/@prbs@any@checker/
async_fifo_prj/sim/work/@prbs@any@checker/_primary.dat
async_fifo_prj/sim/work/@prbs@any@checker/_primary.dbs
async_fifo_prj/sim/work/@prbs@any@checker/_primary.vhd
async_fifo_prj/sim/work/@prbs@any@checker/verilog.prw
async_fifo_prj/sim/work/@prbs@any@checker/verilog.psm
async_fifo_prj/sim/work/@prbs@any@generator/
async_fifo_prj/sim/work/@prbs@any@generator/_primary.dat
async_fifo_prj/sim/work/@prbs@any@generator/_primary.dbs
async_fifo_prj/sim/work/@prbs@any@generator/_primary.vhd
async_fifo_prj/sim/work/@prbs@any@generator/verilog.prw
async_fifo_prj/sim/work/@prbs@any@generator/verilog.psm
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.dat
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.dbs
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/_primary.vhd
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/verilog.prw
async_fifo_prj/sim/work/@top_@my@f@i@f@o_@ctrl/verilog.psm
async_fifo_prj/sim/work/_info
async_fifo_prj/sim/work/_temp/
async_fifo_prj/sim/work/_vmake
async_fifo_prj/sim/work/blk_mem_gen_v2_7/
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.dat
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.dbs
async_fifo_prj/sim/work/blk_mem_gen_v2_7/_primary.vhd
async_fifo_prj/sim/work/blk_mem_gen_v2_7/verilog.prw
async_fifo_prj/sim/work/blk_mem_gen_v2_7/verilog.psm
async_fifo_prj/sim/work/tb_@top_@my@f@i@
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.