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文件名称:PHY_MDIO

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  • 上传时间:
    2015-03-17
  • 文件大小:
    1.06mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

光纤模块实现点对点通信,千兆网传输,基于FPGA,采用Verilog语言进行编程,实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PHY_MDIO/
PHY_MDIO/.sopc_builder/
PHY_MDIO/.sopc_builder/filters.xml
PHY_MDIO/.sopc_builder/install.ptf
PHY_MDIO/.sopc_builder/install2.ptf
PHY_MDIO/.sopc_builder/preferences.xml
PHY_MDIO/clkdiv.v
PHY_MDIO/clkdiv.v.bak
PHY_MDIO/db/
PHY_MDIO/db/altsyncram_2q14.tdf
PHY_MDIO/db/altsyncram_elg1.tdf
PHY_MDIO/db/altsyncram_up14.tdf
PHY_MDIO/db/cmpr_5cc.tdf
PHY_MDIO/db/cmpr_8cc.tdf
PHY_MDIO/db/cmpr_acc.tdf
PHY_MDIO/db/cntr_02j.tdf
PHY_MDIO/db/cntr_0ci.tdf
PHY_MDIO/db/cntr_2ci.tdf
PHY_MDIO/db/cntr_gui.tdf
PHY_MDIO/db/cntr_sbi.tdf
PHY_MDIO/db/decode_rqf.tdf
PHY_MDIO/db/logic_util_heursitic.dat
PHY_MDIO/db/mux_aoc.tdf
PHY_MDIO/db/phy_mdio_controller.db_info
PHY_MDIO/db/phy_mdio_controller.eco.cdb
PHY_MDIO/db/phy_mdio_controller.sld_design_entry.sci
PHY_MDIO/db/prev_cmp_phy_mdio_controller.qmsg
PHY_MDIO/db/sopcb_tb2_unnamed.xml
PHY_MDIO/incremental_db/
PHY_MDIO/incremental_db/compiled_partitions/
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autoh_e4eb1.map.cdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autoh_e4eb1.map.dpi
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autoh_e4eb1.map.hdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autoh_e4eb1.map.kpt
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autoh_e4eb1.map.logdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autos_3e921.map.cdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autos_3e921.map.dpi
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autos_3e921.map.hdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autos_3e921.map.kpt
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.autos_3e921.map.logdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.db_info
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.cdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.dfp
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.hdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.kpt
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.logdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.cmp.rcfdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.cdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.dpi
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.hbdb.cdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.hbdb.hb_info
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.hbdb.hdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.hbdb.sig
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.hdb
PHY_MDIO/incremental_db/compiled_partitions/phy_mdio_controller.root_partition.map.kpt
PHY_MDIO/incremental_db/README
PHY_MDIO/master_0/
PHY_MDIO/master_0.v
PHY_MDIO/master_0/altera_avalon_packets_to_master/
PHY_MDIO/master_0/altera_avalon_packets_to_master/altera_avalon_packets_to_master.v
PHY_MDIO/master_0/altera_avalon_sc_fifo/
PHY_MDIO/master_0/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v
PHY_MDIO/master_0/altera_avalon_st_bytes_to_packets/
PHY_MDIO/master_0/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets.v
PHY_MDIO/master_0/altera_avalon_st_packets_to_bytes/
PHY_MDIO/master_0/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes.v
PHY_MDIO/master_0/altera_jtag_avalon_master/
PHY_MDIO/master_0/altera_jtag_avalon_master/master_0_master_0.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_clock_crosser.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_idle_inserter.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_idle_remover.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_jtag_interface.sdc
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_jtag_interface.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_avalon_st_pipeline_base.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_jtag_dc_streaming.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_jtag_sld_node.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_jtag_streaming.v
PHY_MDIO/master_0/altera_jtag_dc_streaming/altera_pli_streaming.v
PHY_MDIO/master_0/channel_adapter/
PHY_MDIO/master_0/channel_adapter/master_0_b2p_adapter.v
PHY_MDIO/master_0/channel_adapter/master_0_p2b_adapter.v
PHY_MDIO/master_0/timing_adapter/
PHY_MDIO/master_0/timing_adapter/master_0_timing_adt.v
PHY_MDIO/param.h
PHY_MDIO/param.h.bak
PHY_MDIO/phy_mdio.v
PHY_MDIO/phy_mdio.v.bak
PHY_MDIO/phy_mdio_controller.asm.rpt
PHY_MDIO/phy_mdio_controller.bdf
PHY_MDIO/phy_mdio_controller.cdf
PHY_MDIO/phy_mdio_controller.done
PHY_MDIO/phy_mdio_controller.fit.rpt
PHY_MDIO/phy_mdio_controller.fit.smsg
PHY_MDIO/phy_mdio_controller.fit.summary
PHY_MDIO/phy_

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