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verilog 实现的可逆计数器及4-7译码器，实现并行置数，加减计数功能
-verilog achieve reversible counter and 4-7 decoder, set the number of parallelism, subtraction counting function
-verilog achieve reversible counter and 4-7 decoder, set the number of parallelism, subtraction counting function
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decode4_7.v
counter.v
counter.v
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