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文件名称:swp

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  • 上传时间:
    2015-04-04
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    1.5mb
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本文用Verilog语言设计实现SWP数字收发接口的电路设计,并用QuartusⅡ9.1完成调试和功能仿真。在我们的设计中,采用的是分模块的设计方法。设计过程中,我们将首先完成系统架构设计,明确各个分模块的功能。分别实现各模块功能后,再联合所有模块进行总体系统的调试和仿真,最终完成SWP数字收发接口的模块设计。-SWP paper implements digital transceiver interface circuit design using Verilog language design, complete with QuartusⅡ9.1 debugging and functional simulation. In our design, the design method is used in sub-modules. The design process, we will first complete system architecture design, a clear function of each sub-modules. After each module functions were realized, then the union of all modules for debugging and simulation of the overall system, the final completion of the module design SWP digital transceiver interface.
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下载文件列表

swp/
swp/100_11011.vwf
swp/101_00101.vwf
swp/110_01010.vwf
swp/db/
swp/db/logic_util_heursitic.dat
swp/db/prev_cmp_swp.asm.qmsg
swp/db/prev_cmp_swp.fit.qmsg
swp/db/prev_cmp_swp.map.qmsg
swp/db/prev_cmp_swp.qmsg
swp/db/prev_cmp_swp.sim.qmsg
swp/db/prev_cmp_swp.sta.qmsg
swp/db/swp.(0).cnf.cdb
swp/db/swp.(0).cnf.hdb
swp/db/swp.(1).cnf.cdb
swp/db/swp.(1).cnf.hdb
swp/db/swp.(2).cnf.cdb
swp/db/swp.(2).cnf.hdb
swp/db/swp.(3).cnf.cdb
swp/db/swp.(3).cnf.hdb
swp/db/swp.(4).cnf.cdb
swp/db/swp.(4).cnf.hdb
swp/db/swp.(5).cnf.cdb
swp/db/swp.(5).cnf.hdb
swp/db/swp.(6).cnf.cdb
swp/db/swp.(6).cnf.hdb
swp/db/swp.(7).cnf.cdb
swp/db/swp.(7).cnf.hdb
swp/db/swp.(8).cnf.cdb
swp/db/swp.(8).cnf.hdb
swp/db/swp.(9).cnf.cdb
swp/db/swp.(9).cnf.hdb
swp/db/swp.asm.qmsg
swp/db/swp.asm.rdb
swp/db/swp.asm_labs.ddb
swp/db/swp.cbx.xml
swp/db/swp.cmp.bpm
swp/db/swp.cmp.cbp
swp/db/swp.cmp.cdb
swp/db/swp.cmp.ecobp
swp/db/swp.cmp.hdb
swp/db/swp.cmp.kpt
swp/db/swp.cmp.logdb
swp/db/swp.cmp.rdb
swp/db/swp.cmp_merge.kpt
swp/db/swp.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
swp/db/swp.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
swp/db/swp.db_info
swp/db/swp.eco.cdb
swp/db/swp.eds_overflow
swp/db/swp.fit.qmsg
swp/db/swp.fnsim.cdb
swp/db/swp.fnsim.hdb
swp/db/swp.fnsim.qmsg
swp/db/swp.hier_info
swp/db/swp.hif
swp/db/swp.lpc.html
swp/db/swp.lpc.rdb
swp/db/swp.lpc.txt
swp/db/swp.map.bpm
swp/db/swp.map.cdb
swp/db/swp.map.ecobp
swp/db/swp.map.hdb
swp/db/swp.map.kpt
swp/db/swp.map.logdb
swp/db/swp.map.qmsg
swp/db/swp.map_bb.cdb
swp/db/swp.map_bb.hdb
swp/db/swp.map_bb.logdb
swp/db/swp.pre_map.cdb
swp/db/swp.pre_map.hdb
swp/db/swp.rtlv.hdb
swp/db/swp.rtlv_sg.cdb
swp/db/swp.rtlv_sg_swap.cdb
swp/db/swp.sgdiff.cdb
swp/db/swp.sgdiff.hdb
swp/db/swp.sim.cvwf
swp/db/swp.sim.hdb
swp/db/swp.sim.qmsg
swp/db/swp.sim.rdb
swp/db/swp.simfam
swp/db/swp.sld_design_entry.sci
swp/db/swp.sld_design_entry_dsc.sci
swp/db/swp.smart_action.txt
swp/db/swp.sta.qmsg
swp/db/swp.sta.rdb
swp/db/swp.sta_cmp.6_slow_1200mv_85c.tdb
swp/db/swp.syn_hier_info
swp/db/swp.tiscmp.fast_1200mv_0c.ddb
swp/db/swp.tiscmp.slow_1200mv_0c.ddb
swp/db/swp.tiscmp.slow_1200mv_85c.ddb
swp/db/swp.tis_db_list.ddb
swp/db/wed.wsf
swp/decode.v
swp/decode.v.bak
swp/extract.v
swp/extract.v.bak
swp/fdivide10.v
swp/fdivide10.v.bak
swp/fdivide4.v
swp/fdivide4.v.bak
swp/fdivide40.v.bak
swp/incode.v
swp/incode.v.bak
swp/incremental_db/
swp/incremental_db/compiled_partitions/
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.cdb
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.dfp
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.hdb
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.kpt
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.logdb
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.rcfdb
swp/incremental_db/compiled_partitions/swp.root_partition.cmp.re.rcfdb
swp/incremental_db/compiled_partitions/swp.root_partition.map.cdb
swp/incremental_db/compiled_partitions/swp.root_partition.map.dpi
swp/incremental_db/compiled_partitions/swp.root_partition.map.hdb
swp/incremental_db/compiled_partitions/swp.root_partition.map.kpt
swp/incremental_db/README
swp/para_to_serial.v.bak
swp/para_to_serial10_1.v
swp/para_to_serial4_1.v
swp/para_to_serial4_1.v.bak
swp/para_to_serial8_1.v.bak
swp/rx_save.v
swp/rx_save.v.bak
swp/serial_to_para.v
swp/serial_to_para.v.bak
swp/swp.asm.rpt
swp/swp.bsf
swp/swp.done
swp/swp.fit.rpt
swp/swp.fit.smsg
swp/swp.fit.summary
swp/swp.flow.rpt
swp/swp.map.rpt
swp/swp.map.summary
swp/swp.pin
swp/swp.qpf
swp/swp.qsf
swp/swp.qws
swp/swp.sim.rpt
swp/swp.sof
swp/swp.sta.rpt
swp/swp.sta.summary
swp/swp.v
swp/swp.v.bak

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