文件名称:VITERBI_DECODER
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- 上传时间:2015-04-13
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文件大小:123.15kb
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Verilog语言描述的应用于TD-SCDMA中的viterbi译码器rate_1-2_Viterbi_decoder-Applied in TD-SCDMA Verilog language descr iption of the viterbi decoder rate_1-2_Viterbi_decoder
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下载文件列表
Verilog_TD-SCDMA_Viterbi_decoder/sim/modelsim/do.txt
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/block.list
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/compile.bat
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/gtk.bat
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/run_random_data.bat
Verilog_TD-SCDMA_Viterbi_decoder/doc/interface define.txt
Verilog_TD-SCDMA_Viterbi_decoder/doc/Specification.pdf
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog/test_random_data.v
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog/test_fix_data.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/butfly2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/acs2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/brameter2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/delayT.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/glb_def.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/ctrl.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/centrofilo.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/dirtraback.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/decoder.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/tbdir_mod.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/pe.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/smu.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/virtual_mem.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/vit.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/encoder.v
Verilog_TD-SCDMA_Viterbi_decoder/sim/modelsim
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog
Verilog_TD-SCDMA_Viterbi_decoder/sim
Verilog_TD-SCDMA_Viterbi_decoder/doc
Verilog_TD-SCDMA_Viterbi_decoder/bench
Verilog_TD-SCDMA_Viterbi_decoder/rtl
Verilog_TD-SCDMA_Viterbi_decoder
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/block.list
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/compile.bat
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/gtk.bat
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus/run_random_data.bat
Verilog_TD-SCDMA_Viterbi_decoder/doc/interface define.txt
Verilog_TD-SCDMA_Viterbi_decoder/doc/Specification.pdf
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog/test_random_data.v
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog/test_fix_data.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/butfly2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/acs2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/brameter2.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/delayT.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/glb_def.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/ctrl.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/centrofilo.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/dirtraback.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/decoder.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/tbdir_mod.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/pe.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/smu.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/virtual_mem.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/vit.v
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog/encoder.v
Verilog_TD-SCDMA_Viterbi_decoder/sim/modelsim
Verilog_TD-SCDMA_Viterbi_decoder/sim/icarus
Verilog_TD-SCDMA_Viterbi_decoder/bench/verilog
Verilog_TD-SCDMA_Viterbi_decoder/rtl/verilog
Verilog_TD-SCDMA_Viterbi_decoder/sim
Verilog_TD-SCDMA_Viterbi_decoder/doc
Verilog_TD-SCDMA_Viterbi_decoder/bench
Verilog_TD-SCDMA_Viterbi_decoder/rtl
Verilog_TD-SCDMA_Viterbi_decoder
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