文件名称:ex9_cof_M4K_test1
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- 上传时间:2015-04-17
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文件大小:3.87mb
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FPGA器件中通常嵌入一些用户可配置的存储块,此代码是关于基M4K块的单RAM配置仿真实验。 -FPGA devices are usually embedded memory blocks some user-configurable, this code is based on a single M4K block RAM configuration simulation.
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下载文件列表
ex9_cof_M4K_test1/db/altsyncram_oaa1.tdf
ex9_cof_M4K_test1/db/logic_util_heursitic.dat
ex9_cof_M4K_test1/db/mem_cof.db_info
ex9_cof_M4K_test1/db/mem_cof.sld_design_entry.sci
ex9_cof_M4K_test1/db/mem_cof_global_asgn_op.abo
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.asm.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.eda.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.fit.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.map.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.tan.qmsg
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.db_info
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.atm
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.dfp
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.hdbx
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.kpt
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.logdb
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.rcf
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.atm
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.dpi
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.hdbx
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.kpt
ex9_cof_M4K_test1/incremental_db/README
ex9_cof_M4K_test1/mem_cof.asm.rpt
ex9_cof_M4K_test1/mem_cof.done
ex9_cof_M4K_test1/mem_cof.eda.rpt
ex9_cof_M4K_test1/mem_cof.fit.rpt
ex9_cof_M4K_test1/mem_cof.fit.smsg
ex9_cof_M4K_test1/mem_cof.fit.summary
ex9_cof_M4K_test1/mem_cof.flow.rpt
ex9_cof_M4K_test1/mem_cof.map.rpt
ex9_cof_M4K_test1/mem_cof.map.summary
ex9_cof_M4K_test1/mem_cof.pin
ex9_cof_M4K_test1/mem_cof.pof
ex9_cof_M4K_test1/mem_cof.qpf
ex9_cof_M4K_test1/mem_cof.qsf
ex9_cof_M4K_test1/mem_cof.qws
ex9_cof_M4K_test1/mem_cof.sof
ex9_cof_M4K_test1/mem_cof.tan.rpt
ex9_cof_M4K_test1/mem_cof.tan.summary
ex9_cof_M4K_test1/mem_cof.v
ex9_cof_M4K_test1/mem_cof_assignment_defaults.qdf
ex9_cof_M4K_test1/mem_cof_nativelink_simulation.rpt
ex9_cof_M4K_test1/simulation/modelsim/altera_mf.v
ex9_cof_M4K_test1/simulation/modelsim/cyclone_atoms.v
ex9_cof_M4K_test1/simulation/modelsim/mem_cof.sft
ex9_cof_M4K_test1/simulation/modelsim/mem_cof.vo
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_modelsim.xrf
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_run_msim_rtl_verilog.do
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_run_msim_rtl_verilog.do.bak1
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_v.sdo
ex9_cof_M4K_test1/simulation/modelsim/modelsim.ini
ex9_cof_M4K_test1/simulation/modelsim/msim_transcript
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/_info
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/_vmake
ex9_cof_M4K_test1/simulation/modelsim/tb_m4kram.v
ex9_cof_M4K_test1/simulation/modelsim/vsim.wlf
ex9_cof_M4K_test1/simulation/sim_prj/altera_mf.v
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@c@y@c@l@o@n@e_@p@r@i@m_
ex9_cof_M4K_test1/db/logic_util_heursitic.dat
ex9_cof_M4K_test1/db/mem_cof.db_info
ex9_cof_M4K_test1/db/mem_cof.sld_design_entry.sci
ex9_cof_M4K_test1/db/mem_cof_global_asgn_op.abo
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.asm.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.eda.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.fit.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.map.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.qmsg
ex9_cof_M4K_test1/db/prev_cmp_mem_cof.tan.qmsg
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.db_info
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.atm
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.dfp
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.hdbx
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.kpt
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.logdb
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.cmp.rcf
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.atm
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.dpi
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.hdbx
ex9_cof_M4K_test1/incremental_db/compiled_partitions/mem_cof.root_partition.map.kpt
ex9_cof_M4K_test1/incremental_db/README
ex9_cof_M4K_test1/mem_cof.asm.rpt
ex9_cof_M4K_test1/mem_cof.done
ex9_cof_M4K_test1/mem_cof.eda.rpt
ex9_cof_M4K_test1/mem_cof.fit.rpt
ex9_cof_M4K_test1/mem_cof.fit.smsg
ex9_cof_M4K_test1/mem_cof.fit.summary
ex9_cof_M4K_test1/mem_cof.flow.rpt
ex9_cof_M4K_test1/mem_cof.map.rpt
ex9_cof_M4K_test1/mem_cof.map.summary
ex9_cof_M4K_test1/mem_cof.pin
ex9_cof_M4K_test1/mem_cof.pof
ex9_cof_M4K_test1/mem_cof.qpf
ex9_cof_M4K_test1/mem_cof.qsf
ex9_cof_M4K_test1/mem_cof.qws
ex9_cof_M4K_test1/mem_cof.sof
ex9_cof_M4K_test1/mem_cof.tan.rpt
ex9_cof_M4K_test1/mem_cof.tan.summary
ex9_cof_M4K_test1/mem_cof.v
ex9_cof_M4K_test1/mem_cof_assignment_defaults.qdf
ex9_cof_M4K_test1/mem_cof_nativelink_simulation.rpt
ex9_cof_M4K_test1/simulation/modelsim/altera_mf.v
ex9_cof_M4K_test1/simulation/modelsim/cyclone_atoms.v
ex9_cof_M4K_test1/simulation/modelsim/mem_cof.sft
ex9_cof_M4K_test1/simulation/modelsim/mem_cof.vo
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_modelsim.xrf
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_run_msim_rtl_verilog.do
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_run_msim_rtl_verilog.do.bak1
ex9_cof_M4K_test1/simulation/modelsim/mem_cof_v.sdo
ex9_cof_M4K_test1/simulation/modelsim/modelsim.ini
ex9_cof_M4K_test1/simulation/modelsim/msim_transcript
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/mem_cof/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/sys_ram/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/verilog.prw
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/verilog.psm
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.dat
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.dbs
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/tb_m4kram/_primary.vhd
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/_info
ex9_cof_M4K_test1/simulation/modelsim/rtl_work/_vmake
ex9_cof_M4K_test1/simulation/modelsim/tb_m4kram.v
ex9_cof_M4K_test1/simulation/modelsim/vsim.wlf
ex9_cof_M4K_test1/simulation/sim_prj/altera_mf.v
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.asm
ex9_cof_M4K_test1/simulation/sim_prj/cyclone/@c@y@c@l@o@n@e_@p@r@i@m_
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