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文件名称:VerilogHDL_advanced_digital_design_code_Ch5

  • 所属分类：
    VHDL编程
  • 标签属性：
    [WORD]
  • 上传时间：
    2008-10-13
  • 文件大小：
    61.91kb
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    0次
  • 提 供 者：
    lianl******
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Verilog HDL 高级数字设计源码 _chapter5
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VerilogHDL_advanced_digital_design_code_Ch5/adder_task.v
VerilogHDL_advanced_digital_design_code_Ch5/ADDVB_Models_5.doc
VerilogHDL_advanced_digital_design_code_Ch5/add_4cycle.v
VerilogHDL_advanced_digital_design_code_Ch5/AOI_5_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5/AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5/AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5/AOI_5_CA3.v
VerilogHDL_advanced_digital_design_code_Ch5/arithmetic_unit.v
VerilogHDL_advanced_digital_design_code_Ch5/asynch_df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5/Auto_LFSR_ALGO.v
VerilogHDL_advanced_digital_design_code_Ch5/Auto_LFSR_Param.v
VerilogHDL_advanced_digital_design_code_Ch5/Auto_LFSR_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5/barrel_shifter.v
VerilogHDL_advanced_digital_design_code_Ch5/comparator.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_algo.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_CA1.txt
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_ROM.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_2_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5/compare_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/decoder.v
VerilogHDL_advanced_digital_design_code_Ch5/df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5/encoder.v
VerilogHDL_advanced_digital_design_code_Ch5/find_first_one.v
VerilogHDL_advanced_digital_design_code_Ch5/Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5/Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/Majority.v
VerilogHDL_advanced_digital_design_code_Ch5/Majority_4b.v
VerilogHDL_advanced_digital_design_code_Ch5/Mux_4_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/Mux_4_32_case.v
VerilogHDL_advanced_digital_design_code_Ch5/Mux_4_32_if.v
VerilogHDL_advanced_digital_design_code_Ch5/Par_load_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5/pipe_2stage.v
VerilogHDL_advanced_digital_design_code_Ch5/priority.v
VerilogHDL_advanced_digital_design_code_Ch5/Register_File.v
VerilogHDL_advanced_digital_design_code_Ch5/ring_counter.v
VerilogHDL_advanced_digital_design_code_Ch5/Row_Signal.v
VerilogHDL_advanced_digital_design_code_Ch5/Seven_Seg_Display.v
VerilogHDL_advanced_digital_design_code_Ch5/shiftreg_nb.v
VerilogHDL_advanced_digital_design_code_Ch5/shiftreg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5/shiftreg_PA_rev.v
VerilogHDL_advanced_digital_design_code_Ch5/Shift_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5/shift_reg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5/Synchronizer.v
VerilogHDL_advanced_digital_design_code_Ch5/synchro_2.v
VerilogHDL_advanced_digital_design_code_Ch5/tr_latch.v
VerilogHDL_advanced_digital_design_code_Ch5/t_AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5/t_AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5/t_Bin_Cnt_Part_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5/t_Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5/t_Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/t_Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/Universal_Shift_Reg.v
VerilogHDL_advanced_digital_design_code_Ch5/Universal_Shift_Register.v
VerilogHDL_advanced_digital_design_code_Ch5/up_down_counter.v
VerilogHDL_advanced_digital_design_code_Ch5/Up_Down_Implicit1.v
VerilogHDL_advanced_digital_design_code_Ch5/word_aligner.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/adder_task.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/ADDVB_Models_5.doc
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/add_4cycle.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/AOI_5_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/AOI_5_CA3.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/arithmetic_unit.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/asynch_df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/Auto_LFSR_ALGO.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/Auto_LFSR_Param.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/Auto_LFSR_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/barrel_shifter.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/comparator.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_algo.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_CA1.txt
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_ROM.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_2_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/compare_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/decoder.v
VerilogHDL_advanced_digital_design_code_Ch5/_vti_cnf/df_behav.v
VerilogHDL_advanced_digital_design_co

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