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文件名称:CH376

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [Windows] [程序]
  • 上传时间：
    2015-05-07
  • 文件大小：
    6.06mb
  • 已下载：
    1次
  • 提 供 者：
    周***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用VERILOG HDL语言写的usb程序。FPGA芯片用的是ALTERA公司的，编程所用的软件为quartus和nios，USB芯片为CH376.-VERILOG HDL language written with usb program. ALTERA FPGA chip using the company s software program used quartus and nios, USB chip CH376.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CH376/CH376a/.qsys_edit/filters.xml
CH376/CH376a/.qsys_edit/preferences.xml
CH376/CH376a/ch376_controller.v
CH376/CH376a/ch376_controller.v.bak
CH376/CH376a/ch376_controller_hw.tcl
CH376/CH376a/ch376_controller_hw.tcl~
CH376/CH376a/chaqsys/simulation/aldec/rivierapro_setup.tcl
CH376/CH376a/chaqsys/simulation/cadence/cds.lib
CH376/CH376a/chaqsys/simulation/cadence/cds_libs/nios2_qsys.cds.lib
CH376/CH376a/chaqsys/simulation/cadence/hdl.var
CH376/CH376a/chaqsys/simulation/cadence/ncsim_setup.sh
CH376/CH376a/chaqsys/simulation/chaqsys.sip
CH376/CH376a/chaqsys/simulation/chaqsys.v
CH376/CH376a/chaqsys/simulation/mentor/msim_setup.tcl
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys.ocp
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys.sdc
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ic_tag_ram.dat
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ic_tag_ram.hex
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ic_tag_ram.mif
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_jtag_debug_module_sysclk.v
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_jtag_debug_module_tck.v
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_jtag_debug_module_wrapper.v
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_mult_cell.v
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_nios2_waves.do
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ociram_default_contents.dat
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ociram_default_contents.hex
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_ociram_default_contents.mif
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_oci_test_bench.v
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_a.dat
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_a.hex
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_a.mif
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_b.dat
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_b.hex
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_rf_ram_b.mif
CH376/CH376a/chaqsys/simulation/submodules/chaqsys_nios2_qsys_test_bench.v
CH376/CH376a/chaqsys/simulation/synopsys/vcs/vcs_setup.sh
CH376/CH376a/chaqsys/simulation/synopsys/vcsmx/synopsys_sim.setup
CH376/CH376a/chaqsys/simulation/synopsys/vcsmx/vcsmx_setup.sh
CH376/CH376a/chaqsys/synthesis/chaqsys.qip
CH376/CH376a/chaqsys/synthesis/chaqsys.v
CH376/CH376a/chaqsys/synthesis/submodules/altera_avalon_sc_fifo.v
CH376/CH376a/chaqsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_address_alignment.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_arbitrator.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_burst_adapter.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_master_agent.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_master_translator.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_slave_agent.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_slave_translator.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_traffic_limiter.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_merlin_width_adapter.sv
CH376/CH376a/chaqsys/synthesis/submodules/altera_reset_controller.sdc
CH376/CH376a/chaqsys/synthesis/submodules/altera_reset_controller.v
CH376/CH376a/chaqsys/synthesis/submodules/altera_reset_synchronizer.v
CH376/CH376a/chaqsys/synthesis/submodules/ch376_controller.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_addr_router.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_addr_router_001.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_cmd_xbar_demux.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_cmd_xbar_demux_001.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_cmd_xbar_mux.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_id_router.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_id_router_002.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_id_router_003.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_irq_mapper.sv
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_jtag_uart.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys.ocp
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys.sdc
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_ic_tag_ram.mif
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_jtag_debug_module_sysclk.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_jtag_debug_module_tck.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_jtag_debug_module_wrapper.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_mult_cell.v
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_nios2_qsys_ociram_default_contents.mif
CH376/CH376a/chaqsys/synthesis/submodules/chaqsys_ni

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