文件名称:tb_axi4
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- 上传时间:2015-05-19
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文件大小:139kb
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已下载:2次
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介绍如何使用vivado来调用和封装IP核,测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
hdl/
hdl/verilog/
hdl/verilog/axi_lite_master.v
hdl/verilog/axi_lite_slave.v
hdl/verilog/axi_master.v
hdl/verilog/axi_slave.v
hdl/verilog/axi_stream_master.v
hdl/verilog/axi_stream_slave.v
ip_repo_complete/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0.zip
ip_repo_complete/vv_index.xml
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/verilog/axi_master.v
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/xgui/axi_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/verilog/axi_lite_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/xgui/axi_lite_slave_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/verilog/axi_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/xgui/axi_slave_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/verilog/axi_lite_master.v
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/xgui/axi_lite_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/verilog/axi_stream_master.v
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/xgui/axi_stream_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/verilog/axi_stream_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/xgui/axi_stream_slave_v1_0.tcl
readme.txt
source.tcl
tb/
tb/verilog/
tb/verilog/axi_stream_system_wrapper_tb.v
tb/verilog/axi_system_wrapper_tb.v
tb/verilog/lite_system_wrapper_tb.v
hdl/verilog/
hdl/verilog/axi_lite_master.v
hdl/verilog/axi_lite_slave.v
hdl/verilog/axi_master.v
hdl/verilog/axi_slave.v
hdl/verilog/axi_stream_master.v
hdl/verilog/axi_stream_slave.v
ip_repo_complete/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0.zip
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0.zip
ip_repo_complete/vv_index.xml
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/verilog/axi_master.v
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_master_1.0/xgui/axi_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/verilog/axi_lite_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_lite_slave_1.0/xgui/axi_lite_slave_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/verilog/axi_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_slave_1.0/xgui/axi_slave_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/verilog/axi_lite_master.v
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_lite_master_1.0/xgui/axi_lite_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/verilog/axi_stream_master.v
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_stream_master_1.0/xgui/axi_stream_master_v1_0.tcl
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/component.xml
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/verilog/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/verilog/axi_stream_slave.v
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/xgui/
ip_repo_complete/YourCompanyName.com_user_axi_stream_slave_1.0/xgui/axi_stream_slave_v1_0.tcl
readme.txt
source.tcl
tb/
tb/verilog/
tb/verilog/axi_stream_system_wrapper_tb.v
tb/verilog/axi_system_wrapper_tb.v
tb/verilog/lite_system_wrapper_tb.v
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