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文件名称:DesVer

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  • 上传时间:
    2015-06-06
  • 文件大小:
    757.08kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

实现FPGA中执行DES算法,通过RS232实现数据传送功能 -Implement FPGA DES algorithm is d, data transfer function via RS232
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DesVer/
DesVer/Des.cr.mti
DesVer/Des.mpf
DesVer/Des.v
DesVer/IP.v
DesVer/IP_ni.v
DesVer/Modelsim_10[neubt]Modelsim_se_10.0a_Crackerworkspacewin64worka.txt
DesVer/contrl.v
DesVer/des_f.v
DesVer/des_top.v
DesVer/key_get.v
DesVer/pc_1.v
DesVer/s1.v
DesVer/s2.v
DesVer/s3.v
DesVer/s4.v
DesVer/s5.v
DesVer/s6.v
DesVer/s7.v
DesVer/s8.v
DesVer/testbench.v
DesVer/vsim.wlf
DesVer/work/
DesVer/work/@des/
DesVer/work/@des/_primary.dat
DesVer/work/@des/_primary.dbs
DesVer/work/@des/_primary.vhd
DesVer/work/@i@p/
DesVer/work/@i@p/_primary.dat
DesVer/work/@i@p/_primary.dbs
DesVer/work/@i@p/_primary.vhd
DesVer/work/@i@p/verilog.asm64
DesVer/work/@i@p/verilog.rw64
DesVer/work/@i@p_ni/
DesVer/work/@i@p_ni/_primary.dat
DesVer/work/@i@p_ni/_primary.dbs
DesVer/work/@i@p_ni/_primary.vhd
DesVer/work/@i@p_ni/verilog.asm64
DesVer/work/@i@p_ni/verilog.rw64
DesVer/work/_info
DesVer/work/_temp/
DesVer/work/_temp/vlog2b2xgf
DesVer/work/_temp/vlog3ej8t4
DesVer/work/_temp/vlogt34zny
DesVer/work/_vmake
DesVer/work/ck/
DesVer/work/ck/_primary.dat
DesVer/work/ck/_primary.dbs
DesVer/work/ck/_primary.vhd
DesVer/work/contrl/
DesVer/work/contrl/_primary.dat
DesVer/work/contrl/_primary.dbs
DesVer/work/contrl/_primary.vhd
DesVer/work/contrl/verilog.asm64
DesVer/work/contrl/verilog.rw64
DesVer/work/des_f/
DesVer/work/des_f/_primary.dat
DesVer/work/des_f/_primary.dbs
DesVer/work/des_f/_primary.vhd
DesVer/work/des_f/verilog.asm64
DesVer/work/des_f/verilog.rw64
DesVer/work/des_top/
DesVer/work/des_top/_primary.dat
DesVer/work/des_top/_primary.dbs
DesVer/work/des_top/_primary.vhd
DesVer/work/des_top/verilog.asm64
DesVer/work/des_top/verilog.rw64
DesVer/work/key_get/
DesVer/work/key_get/_primary.dat
DesVer/work/key_get/_primary.dbs
DesVer/work/key_get/_primary.vhd
DesVer/work/key_get/verilog.asm64
DesVer/work/key_get/verilog.rw64
DesVer/work/my_uart_rx/
DesVer/work/my_uart_rx/_primary.dat
DesVer/work/my_uart_rx/_primary.dbs
DesVer/work/my_uart_rx/_primary.vhd
DesVer/work/my_uart_tx/
DesVer/work/my_uart_tx/_primary.dat
DesVer/work/my_uart_tx/_primary.dbs
DesVer/work/my_uart_tx/_primary.vhd
DesVer/work/pc_1/
DesVer/work/pc_1/_primary.dat
DesVer/work/pc_1/_primary.dbs
DesVer/work/pc_1/_primary.vhd
DesVer/work/pc_1/verilog.asm64
DesVer/work/pc_1/verilog.rw64
DesVer/work/s1/
DesVer/work/s1/_primary.dat
DesVer/work/s1/_primary.dbs
DesVer/work/s1/_primary.vhd
DesVer/work/s1/verilog.asm64
DesVer/work/s1/verilog.rw64
DesVer/work/s2/
DesVer/work/s2/_primary.dat
DesVer/work/s2/_primary.dbs
DesVer/work/s2/_primary.vhd
DesVer/work/s2/verilog.asm64
DesVer/work/s2/verilog.rw64
DesVer/work/s3/
DesVer/work/s3/_primary.dat
DesVer/work/s3/_primary.dbs
DesVer/work/s3/_primary.vhd
DesVer/work/s3/verilog.asm64
DesVer/work/s3/verilog.rw64
DesVer/work/s4/
DesVer/work/s4/_primary.dat
DesVer/work/s4/_primary.dbs
DesVer/work/s4/_primary.vhd
DesVer/work/s4/verilog.asm64
DesVer/work/s4/verilog.rw64
DesVer/work/s5/
DesVer/work/s5/_primary.dat
DesVer/work/s5/_primary.dbs
DesVer/work/s5/_primary.vhd
DesVer/work/s5/verilog.asm64
DesVer/work/s5/verilog.rw64
DesVer/work/s6/
DesVer/work/s6/_primary.dat
DesVer/work/s6/_primary.dbs
DesVer/work/s6/_primary.vhd
DesVer/work/s6/verilog.asm64
DesVer/work/s6/verilog.rw64
DesVer/work/s7/
DesVer/work/s7/_primary.dat
DesVer/work/s7/_primary.dbs
DesVer/work/s7/_primary.vhd
DesVer/work/s7/verilog.asm64
DesVer/work/s7/verilog.rw64
DesVer/work/s8/
DesVer/work/s8/_primary.dat
DesVer/work/s8/_primary.dbs
DesVer/work/s8/_primary.vhd
DesVer/work/s8/verilog.asm64
DesVer/work/s8/verilog.rw64
DesVer/work/speed_select/
DesVer/work/speed_select/_primary.dat
DesVer/work/speed_select/_primary.dbs
DesVer/work/speed_select/_primary.vhd
DesVer/work/testbench/
DesVer/work/testbench/_primary.dat
DesVer/work/testbench/_primary.dbs
DesVer/work/testbench/_primary.vhd
DesVer/work/testbench/verilog.asm64
DesVer/work/testbench/verilog.rw64

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