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文件名称:wulian_dingwenxin_3012204216

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-06-14
  • 文件大小：
    1.34mb
  • 已下载：
    0次
  • 提 供 者：
    李****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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基于quartus2的环境，做的认真，实现了微波炉的开关温度设置等-Quartus2 based environment, do seriously, to achieve a switching temperature microwave ovens, etc.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

wulian_dingwenxin_3012204216/VHDL/
wulian_dingwenxin_3012204216/VHDL/A1.qpf
wulian_dingwenxin_3012204216/VHDL/A1.qsf
wulian_dingwenxin_3012204216/VHDL/A1.qws
wulian_dingwenxin_3012204216/VHDL/A1.vhd
wulian_dingwenxin_3012204216/VHDL/A1_nativelink_simulation.rpt
wulian_dingwenxin_3012204216/VHDL/db/
wulian_dingwenxin_3012204216/VHDL/db/A1.(0).cnf.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.(0).cnf.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.asm.qmsg
wulian_dingwenxin_3012204216/VHDL/db/A1.asm.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.asm_labs.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.cbx.xml
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.bpm
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.idb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.kpt
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.logdb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp_merge.kpt
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp0.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp1.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.cmp2.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.db_info
wulian_dingwenxin_3012204216/VHDL/db/A1.eda.qmsg
wulian_dingwenxin_3012204216/VHDL/db/A1.fit.qmsg
wulian_dingwenxin_3012204216/VHDL/db/A1.hier_info
wulian_dingwenxin_3012204216/VHDL/db/A1.hif
wulian_dingwenxin_3012204216/VHDL/db/A1.ipinfo
wulian_dingwenxin_3012204216/VHDL/db/A1.lpc.html
wulian_dingwenxin_3012204216/VHDL/db/A1.lpc.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.lpc.txt
wulian_dingwenxin_3012204216/VHDL/db/A1.map.ammdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map.bpm
wulian_dingwenxin_3012204216/VHDL/db/A1.map.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map.kpt
wulian_dingwenxin_3012204216/VHDL/db/A1.map.logdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map.qmsg
wulian_dingwenxin_3012204216/VHDL/db/A1.map.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map_bb.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map_bb.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.map_bb.logdb
wulian_dingwenxin_3012204216/VHDL/db/A1.pre_map.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.pti_db_list.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.root_partition.map.reg_db.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.routing.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.rtlv.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.rtlv_sg.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.rtlv_sg_swap.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.sgdiff.cdb
wulian_dingwenxin_3012204216/VHDL/db/A1.sgdiff.hdb
wulian_dingwenxin_3012204216/VHDL/db/A1.sld_design_entry.sci
wulian_dingwenxin_3012204216/VHDL/db/A1.sld_design_entry_dsc.sci
wulian_dingwenxin_3012204216/VHDL/db/A1.smart_action.txt
wulian_dingwenxin_3012204216/VHDL/db/A1.sta.qmsg
wulian_dingwenxin_3012204216/VHDL/db/A1.sta.rdb
wulian_dingwenxin_3012204216/VHDL/db/A1.sta_cmp.7A_slow.tdb
wulian_dingwenxin_3012204216/VHDL/db/A1.syn_hier_info
wulian_dingwenxin_3012204216/VHDL/db/A1.tis_db_list.ddb
wulian_dingwenxin_3012204216/VHDL/db/A1.tmw_info
wulian_dingwenxin_3012204216/VHDL/db/A1.vpr.ammdb
wulian_dingwenxin_3012204216/VHDL/db/logic_util_heursitic.dat
wulian_dingwenxin_3012204216/VHDL/db/prev_cmp_A1.qmsg
wulian_dingwenxin_3012204216/VHDL/incremental_db/
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.db_info
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.ammdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.cdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.dfp
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.hdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.kpt
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.logdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.cmp.rcfdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.cdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.dpi
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.hbdb.cdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.hbdb.hb_info
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.hbdb.hdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.hbdb.sig
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.hdb
wulian_dingwenxin_3012204216/VHDL/incremental_db/compiled_partitions/A1.root_partition.map.kpt
wulian_dingwenxin_3012204216/VHDL/incremental_db/README
wulian_dingwenxin_3012204216/VHDL/output_files/
wulian_dingwenxin_3012204216/VHDL/output_files/A1.asm.rpt
wulian_dingwenxin_3012204216/VH

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