文件名称:emac_standard
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- 上传时间:2015-06-29
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文件大小:1.36mb
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基于Xilinx的V5芯片设计的网络MAC层接口程序,可以与计算机进行网络通信,可根据自己需要进行裁剪定制,已通过板卡的实际测试。-Chip design based on Xilinx s network V5 MAC layer interface, can communicate with the computer network, can be tailored to customize according to their needs, the board has passed the actual test.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
emac_standard/
emac_standard/.recordref
emac_standard/.recordref_modgen
emac_standard/AutoConstraint_v5_emac_v1_5_example_design.sdc
emac_standard/_mh_info
emac_standard/_verilog_hintfile
emac_standard/_xmsgs/
emac_standard/_xmsgs/pn_parser.xmsgs
emac_standard/backup/
emac_standard/client/
emac_standard/client/address_swap_module_8.vhd
emac_standard/client/fifo/
emac_standard/client/fifo/eth_fifo_8.vhd
emac_standard/client/fifo/rx_client_fifo_8.vhd
emac_standard/client/fifo/tx_client_fifo_8.vhd
emac_standard/coreip/
emac_standard/dm/
emac_standard/dm/layer0.xdm
emac_standard/emac_standard.gise
emac_standard/emac_standard.xise
emac_standard/ipcore_dir/
emac_standard/ipcore_dir/_xmsgs/
emac_standard/ipcore_dir/_xmsgs/cg.xmsgs
emac_standard/ipcore_dir/coregen.log
emac_standard/ipcore_dir/create_GTP.tcl
emac_standard/ipcore_dir/tmp/
emac_standard/ipcore_dir/tmp/_cg/
emac_standard/ipcore_dir/tmp/_cg/xil_11192_5.in
emac_standard/ipcore_dir/tmp/_cg/xil_11192_5.out
emac_standard/iseconfig/
emac_standard/iseconfig/emac_standard.projectmgr
emac_standard/iseconfig/v5_emac_v1_5_example_design.xreport
emac_standard/layer0.srs
emac_standard/layer0.tlg
emac_standard/physical/
emac_standard/physical/gtp_dual_1000X.vhd
emac_standard/physical/rocketio_wrapper_gtp.vhd
emac_standard/physical/rocketio_wrapper_gtp_tile.vhd
emac_standard/physical/rx_elastic_buffer.vhd
emac_standard/physical_plus/
emac_standard/physical_plus/syntmp/
emac_standard/rpt_v5_emac_v1_5_example_design.areasrr
emac_standard/rpt_v5_emac_v1_5_example_design_areasrr.htm
emac_standard/run_ise.tcl
emac_standard/run_options.txt
emac_standard/scratchproject.prs
emac_standard/stdout.log
emac_standard/synlog/
emac_standard/synlog/report/
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_warnings.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_area_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_errors.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_generated_clk.rpt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_hier_area.csv
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_hier_area_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_opt_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_resourceusage.rpt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_timing_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_warnings.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_errors.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_warnings.txt
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.srr
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.srr_Min
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.szr
emac_standard/synlog/v5_emac_v1_5_example_design_premap.srr
emac_standard/synlog/v5_emac_v1_5_example_design_premap.szr
emac_standard/synplicity.ucf
emac_standard/syntmp/
emac_standard/syntmp/cmdrec_compiler.log
emac_standard/syntmp/cmdrec_fpga_mapper.log
emac_standard/syntmp/cmdrec_premap.log
emac_standard/syntmp/namekey.txt
emac_standard/syntmp/run_option.xml
emac_standard/syntmp/unisim.tlg
emac_standard/syntmp/unisim.v
emac_standard/syntmp/v5_emac_v1_5_example_design.msg
emac_standard/syntmp/v5_emac_v1_5_example_design.plg
emac_standard/synwork/
emac_standard/synwork/v5_emac_v1_5_example_design_compiler.srs
emac_standard/synwork/v5_emac_v1_5_example_design_premap.fse
emac_standard/synwork/v5_emac_v1_5_example_design_premap.srd
emac_standard/traplog.tlg
emac_standard/v5_emac_v1_5.vhd
emac_standard/v5_emac_v1_5_block.vhd
emac_standard/v5_emac_v1_5_example_design.cmd_log
emac_standard/v5_emac_v1_5_example_design.edn
emac_standard/v5_emac_v1_5_example_design.fse
emac_standard/v5_emac_v1_5_example_design.map
emac_standard/v5_emac_v1_5_example_design.ncf
emac_standard/v5_emac_v1_5_example_design.prj
emac_standard/v5_emac_v1_5_example_design.sap
emac_standard/v5_emac_v1_5_example_design.sdc
emac_standard/v5_emac_v1_5_example_design.srd
emac_standard/v5_emac_v1_5_example_design.srl
emac_standard/v5_emac_v1_5_example_design.srm
emac_standard/v5_emac_v1_5_example_design.srr
emac_standard/v5_emac_v1_5_example_design.srs
emac_standard/v5_emac_v1_5_example_design.szr
emac_standard/v5_emac_v1_5_example_design.ucf
emac_standard/v5_emac_v1_5_example_design.vhd
emac_standard/v5_emac_v1_5_example_design_bitgen.xwbt
emac_standard/v5_emac_v1_5_example_design_compile.tcl
emac_standard/v5_emac_v1_5_example_design_guide.ncd
emac_standard/v5_emac_v1_5_ex
emac_standard/.recordref
emac_standard/.recordref_modgen
emac_standard/AutoConstraint_v5_emac_v1_5_example_design.sdc
emac_standard/_mh_info
emac_standard/_verilog_hintfile
emac_standard/_xmsgs/
emac_standard/_xmsgs/pn_parser.xmsgs
emac_standard/backup/
emac_standard/client/
emac_standard/client/address_swap_module_8.vhd
emac_standard/client/fifo/
emac_standard/client/fifo/eth_fifo_8.vhd
emac_standard/client/fifo/rx_client_fifo_8.vhd
emac_standard/client/fifo/tx_client_fifo_8.vhd
emac_standard/coreip/
emac_standard/dm/
emac_standard/dm/layer0.xdm
emac_standard/emac_standard.gise
emac_standard/emac_standard.xise
emac_standard/ipcore_dir/
emac_standard/ipcore_dir/_xmsgs/
emac_standard/ipcore_dir/_xmsgs/cg.xmsgs
emac_standard/ipcore_dir/coregen.log
emac_standard/ipcore_dir/create_GTP.tcl
emac_standard/ipcore_dir/tmp/
emac_standard/ipcore_dir/tmp/_cg/
emac_standard/ipcore_dir/tmp/_cg/xil_11192_5.in
emac_standard/ipcore_dir/tmp/_cg/xil_11192_5.out
emac_standard/iseconfig/
emac_standard/iseconfig/emac_standard.projectmgr
emac_standard/iseconfig/v5_emac_v1_5_example_design.xreport
emac_standard/layer0.srs
emac_standard/layer0.tlg
emac_standard/physical/
emac_standard/physical/gtp_dual_1000X.vhd
emac_standard/physical/rocketio_wrapper_gtp.vhd
emac_standard/physical/rocketio_wrapper_gtp_tile.vhd
emac_standard/physical/rx_elastic_buffer.vhd
emac_standard/physical_plus/
emac_standard/physical_plus/syntmp/
emac_standard/rpt_v5_emac_v1_5_example_design.areasrr
emac_standard/rpt_v5_emac_v1_5_example_design_areasrr.htm
emac_standard/run_ise.tcl
emac_standard/run_options.txt
emac_standard/scratchproject.prs
emac_standard/stdout.log
emac_standard/synlog/
emac_standard/synlog/report/
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_compiler_warnings.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_area_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_errors.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_generated_clk.rpt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_hier_area.csv
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_hier_area_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_opt_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_resourceusage.rpt
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_timing_report.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_fpga_mapper_warnings.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_errors.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_notes.txt
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_runstatus.xml
emac_standard/synlog/report/v5_emac_v1_5_example_design_premap_warnings.txt
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.srr
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.srr_Min
emac_standard/synlog/v5_emac_v1_5_example_design_fpga_mapper.szr
emac_standard/synlog/v5_emac_v1_5_example_design_premap.srr
emac_standard/synlog/v5_emac_v1_5_example_design_premap.szr
emac_standard/synplicity.ucf
emac_standard/syntmp/
emac_standard/syntmp/cmdrec_compiler.log
emac_standard/syntmp/cmdrec_fpga_mapper.log
emac_standard/syntmp/cmdrec_premap.log
emac_standard/syntmp/namekey.txt
emac_standard/syntmp/run_option.xml
emac_standard/syntmp/unisim.tlg
emac_standard/syntmp/unisim.v
emac_standard/syntmp/v5_emac_v1_5_example_design.msg
emac_standard/syntmp/v5_emac_v1_5_example_design.plg
emac_standard/synwork/
emac_standard/synwork/v5_emac_v1_5_example_design_compiler.srs
emac_standard/synwork/v5_emac_v1_5_example_design_premap.fse
emac_standard/synwork/v5_emac_v1_5_example_design_premap.srd
emac_standard/traplog.tlg
emac_standard/v5_emac_v1_5.vhd
emac_standard/v5_emac_v1_5_block.vhd
emac_standard/v5_emac_v1_5_example_design.cmd_log
emac_standard/v5_emac_v1_5_example_design.edn
emac_standard/v5_emac_v1_5_example_design.fse
emac_standard/v5_emac_v1_5_example_design.map
emac_standard/v5_emac_v1_5_example_design.ncf
emac_standard/v5_emac_v1_5_example_design.prj
emac_standard/v5_emac_v1_5_example_design.sap
emac_standard/v5_emac_v1_5_example_design.sdc
emac_standard/v5_emac_v1_5_example_design.srd
emac_standard/v5_emac_v1_5_example_design.srl
emac_standard/v5_emac_v1_5_example_design.srm
emac_standard/v5_emac_v1_5_example_design.srr
emac_standard/v5_emac_v1_5_example_design.srs
emac_standard/v5_emac_v1_5_example_design.szr
emac_standard/v5_emac_v1_5_example_design.ucf
emac_standard/v5_emac_v1_5_example_design.vhd
emac_standard/v5_emac_v1_5_example_design_bitgen.xwbt
emac_standard/v5_emac_v1_5_example_design_compile.tcl
emac_standard/v5_emac_v1_5_example_design_guide.ncd
emac_standard/v5_emac_v1_5_ex
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