文件名称:0714
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- 上传时间:2015-07-14
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文件大小:564.94kb
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介绍说明--下载内容来自于网络,使用问题请自行百度
这是一个简单的基于VHDL的初学者编写的功能丰富的电子钟.-This is a simple VHDL based program for beginners to write a rich electronic clock.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
0714/
0714/db/
0714/db/d_clk.(0).cnf.cdb
0714/db/d_clk.(0).cnf.hdb
0714/db/d_clk.asm.qmsg
0714/db/d_clk.cbx.xml
0714/db/d_clk.cmp.cdb
0714/db/d_clk.cmp.hdb
0714/db/d_clk.cmp.kpt
0714/db/d_clk.cmp.logdb
0714/db/d_clk.cmp.rdb
0714/db/d_clk.cmp.tdb
0714/db/d_clk.cmp0.ddb
0714/db/d_clk.dbp
0714/db/d_clk.db_info
0714/db/d_clk.eco.cdb
0714/db/d_clk.eds_overflow
0714/db/d_clk.fit.qmsg
0714/db/d_clk.hier_info
0714/db/d_clk.hif
0714/db/d_clk.map.cdb
0714/db/d_clk.map.hdb
0714/db/d_clk.map.logdb
0714/db/d_clk.map.qmsg
0714/db/d_clk.pre_map.cdb
0714/db/d_clk.pre_map.hdb
0714/db/d_clk.psp
0714/db/d_clk.rtlv.hdb
0714/db/d_clk.rtlv_sg.cdb
0714/db/d_clk.rtlv_sg_swap.cdb
0714/db/d_clk.sgdiff.cdb
0714/db/d_clk.sgdiff.hdb
0714/db/d_clk.signalprobe.cdb
0714/db/d_clk.sim.hdb
0714/db/d_clk.sim.qmsg
0714/db/d_clk.sim.rdb
0714/db/d_clk.sim.vwf
0714/db/d_clk.sld_design_entry.sci
0714/db/d_clk.sld_design_entry_dsc.sci
0714/db/d_clk.syn_hier_info
0714/db/d_clk.tan.qmsg
0714/db/wed.zsf
0714/d_clk.asm.rpt
0714/d_clk.done
0714/d_clk.dpf
0714/d_clk.fit.rpt
0714/d_clk.fit.smsg
0714/d_clk.fit.summary
0714/d_clk.flow.rpt
0714/d_clk.map.rpt
0714/d_clk.map.summary
0714/d_clk.pin
0714/d_clk.pof
0714/d_clk.qpf
0714/d_clk.qsf
0714/d_clk.qws
0714/d_clk.sim.rpt
0714/d_clk.sof
0714/d_clk.tan.rpt
0714/d_clk.tan.summary
0714/d_clk.vhd
0714/d_clk.vwf
0714/db/
0714/db/d_clk.(0).cnf.cdb
0714/db/d_clk.(0).cnf.hdb
0714/db/d_clk.asm.qmsg
0714/db/d_clk.cbx.xml
0714/db/d_clk.cmp.cdb
0714/db/d_clk.cmp.hdb
0714/db/d_clk.cmp.kpt
0714/db/d_clk.cmp.logdb
0714/db/d_clk.cmp.rdb
0714/db/d_clk.cmp.tdb
0714/db/d_clk.cmp0.ddb
0714/db/d_clk.dbp
0714/db/d_clk.db_info
0714/db/d_clk.eco.cdb
0714/db/d_clk.eds_overflow
0714/db/d_clk.fit.qmsg
0714/db/d_clk.hier_info
0714/db/d_clk.hif
0714/db/d_clk.map.cdb
0714/db/d_clk.map.hdb
0714/db/d_clk.map.logdb
0714/db/d_clk.map.qmsg
0714/db/d_clk.pre_map.cdb
0714/db/d_clk.pre_map.hdb
0714/db/d_clk.psp
0714/db/d_clk.rtlv.hdb
0714/db/d_clk.rtlv_sg.cdb
0714/db/d_clk.rtlv_sg_swap.cdb
0714/db/d_clk.sgdiff.cdb
0714/db/d_clk.sgdiff.hdb
0714/db/d_clk.signalprobe.cdb
0714/db/d_clk.sim.hdb
0714/db/d_clk.sim.qmsg
0714/db/d_clk.sim.rdb
0714/db/d_clk.sim.vwf
0714/db/d_clk.sld_design_entry.sci
0714/db/d_clk.sld_design_entry_dsc.sci
0714/db/d_clk.syn_hier_info
0714/db/d_clk.tan.qmsg
0714/db/wed.zsf
0714/d_clk.asm.rpt
0714/d_clk.done
0714/d_clk.dpf
0714/d_clk.fit.rpt
0714/d_clk.fit.smsg
0714/d_clk.fit.summary
0714/d_clk.flow.rpt
0714/d_clk.map.rpt
0714/d_clk.map.summary
0714/d_clk.pin
0714/d_clk.pof
0714/d_clk.qpf
0714/d_clk.qsf
0714/d_clk.qws
0714/d_clk.sim.rpt
0714/d_clk.sof
0714/d_clk.tan.rpt
0714/d_clk.tan.summary
0714/d_clk.vhd
0714/d_clk.vwf
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