ddr3_demo_verilog/
ddr3_demo_verilog/core/
ddr3_demo_verilog/core/ddr3core.lpc
ddr3_demo_verilog/resource/
ddr3_demo_verilog/resource/16bit_support/
ddr3_demo_verilog/resource/16bit_support/core/
ddr3_demo_verilog/resource/16bit_support/core/ddr3core.lpc
ddr3_demo_verilog/resource/16bit_support/lpf/
ddr3_demo_verilog/resource/16bit_support/lpf/ecp3_ddr3.lpf
ddr3_demo_verilog/resource/32bit_support/
ddr3_demo_verilog/resource/32bit_support/core/
ddr3_demo_verilog/resource/32bit_support/core/ddr3core.lpc
ddr3_demo_verilog/resource/32bit_support/lpf/
ddr3_demo_verilog/resource/32bit_support/lpf/ecp3_ddr3.lpf
ddr3_demo_verilog/resource/64bit_dual_rank/
ddr3_demo_verilog/resource/64bit_dual_rank/core/
ddr3_demo_verilog/resource/64bit_dual_rank/core/ddr3core.lpc
ddr3_demo_verilog/resource/64bit_dual_rank/lpf/
ddr3_demo_verilog/resource/64bit_dual_rank/lpf/ecp3_ddr3.lpf
ddr3_demo_verilog/resource/bitstream/
ddr3_demo_verilog/resource/bitstream/64bit/
ddr3_demo_verilog/resource/bitstream/64bit/ecp3_ddr3_impl1.bit
ddr3_demo_verilog/resource/doc/
ddr3_demo_verilog/resource/doc/readme.txt
ddr3_demo_verilog/user_logic/
ddr3_demo_verilog/user_logic/par/
ddr3_demo_verilog/user_logic/par/diamond/
ddr3_demo_verilog/user_logic/par/diamond/.run_manager.ini
ddr3_demo_verilog/user_logic/par/diamond/ecp3_ddr3.ldf
ddr3_demo_verilog/user_logic/par/diamond/ecp3_ddr3.lpf
ddr3_demo_verilog/user_logic/par/diamond/ecp3_ddr3.pty
ddr3_demo_verilog/user_logic/par/diamond/ecp3_ddr3.tpf
ddr3_demo_verilog/user_logic/par/diamond/impl1/
ddr3_demo_verilog/user_logic/par/diamond/impl1/.build_status
ddr3_demo_verilog/user_logic/par/diamond/impl1/ecp3_ddr3_impl1_summary.html
ddr3_demo_verilog/user_logic/par/diamond/post_route_trace.prf
ddr3_demo_verilog/user_logic/par/diamond/reportview.xml
ddr3_demo_verilog/user_logic/par/diamond/Strategy1.sty
ddr3_demo_verilog/user_logic/sim/
ddr3_demo_verilog/user_logic/sim/aldec/
ddr3_demo_verilog/user_logic/sim/aldec/ddr3_ecp3_demo.do
ddr3_demo_verilog/user_logic/sim/aldec/wave.do
ddr3_demo_verilog/user_logic/sim/modelsim/
ddr3_demo_verilog/user_logic/sim/modelsim/ddr3_ecp3_demo.do
ddr3_demo_verilog/user_logic/sim/modelsim/wave.do
ddr3_demo_verilog/user_logic/src/
ddr3_demo_verilog/user_logic/src/data_gen_chk.v
ddr3_demo_verilog/user_logic/src/ddr3_test_params.v
ddr3_demo_verilog/user_logic/src/ddr3_test_top.v
ddr3_demo_verilog/user_logic/src/ddr_ulogic.v
ddr3_demo_verilog/user_logic/src/debounce.v
ddr3_demo_verilog/user_logic/src/lfsr128.v
ddr3_demo_verilog/user_logic/src/lfsr32.v
ddr3_demo_verilog/user_logic/testbench/
ddr3_demo_verilog/user_logic/testbench/ddr3_test_top_tb.v