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文件名称:UART_proj

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2015-07-30
  • 文件大小：
    6.81mb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

串口发送接受功能，上位机发送消息给FPGA，FPGA接收后将相同的消息发送至上位机。-A serial port to send in function, PC sends a message to the FPGA, FPGA after receiving the same message is sent first place machine.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART_proj/pro/db/logic_util_heursitic.dat
UART_proj/pro/db/prev_cmp_UART_top.qmsg
UART_proj/pro/db/UART_top.(0).cnf.cdb
UART_proj/pro/db/UART_top.(0).cnf.hdb
UART_proj/pro/db/UART_top.(1).cnf.cdb
UART_proj/pro/db/UART_top.(1).cnf.hdb
UART_proj/pro/db/UART_top.(2).cnf.cdb
UART_proj/pro/db/UART_top.(2).cnf.hdb
UART_proj/pro/db/UART_top.(3).cnf.cdb
UART_proj/pro/db/UART_top.(3).cnf.hdb
UART_proj/pro/db/UART_top.(4).cnf.cdb
UART_proj/pro/db/UART_top.(4).cnf.hdb
UART_proj/pro/db/UART_top.(5).cnf.cdb
UART_proj/pro/db/UART_top.(5).cnf.hdb
UART_proj/pro/db/UART_top.asm.qmsg
UART_proj/pro/db/UART_top.asm.rdb
UART_proj/pro/db/UART_top.asm_labs.ddb
UART_proj/pro/db/UART_top.cbx.xml
UART_proj/pro/db/UART_top.cmp.bpm
UART_proj/pro/db/UART_top.cmp.cdb
UART_proj/pro/db/UART_top.cmp.hdb
UART_proj/pro/db/UART_top.cmp.idb
UART_proj/pro/db/UART_top.cmp.kpt
UART_proj/pro/db/UART_top.cmp.logdb
UART_proj/pro/db/UART_top.cmp.rdb
UART_proj/pro/db/UART_top.cmp0.ddb
UART_proj/pro/db/UART_top.cmp1.ddb
UART_proj/pro/db/UART_top.cmp2.ddb
UART_proj/pro/db/UART_top.cmp_merge.kpt
UART_proj/pro/db/UART_top.db_info
UART_proj/pro/db/UART_top.fit.qmsg
UART_proj/pro/db/UART_top.hier_info
UART_proj/pro/db/UART_top.hif
UART_proj/pro/db/UART_top.ipinfo
UART_proj/pro/db/UART_top.lpc.html
UART_proj/pro/db/UART_top.lpc.rdb
UART_proj/pro/db/UART_top.lpc.txt
UART_proj/pro/db/UART_top.map.ammdb
UART_proj/pro/db/UART_top.map.bpm
UART_proj/pro/db/UART_top.map.cdb
UART_proj/pro/db/UART_top.map.hdb
UART_proj/pro/db/UART_top.map.kpt
UART_proj/pro/db/UART_top.map.logdb
UART_proj/pro/db/UART_top.map.qmsg
UART_proj/pro/db/UART_top.map.rdb
UART_proj/pro/db/UART_top.map_bb.cdb
UART_proj/pro/db/UART_top.map_bb.hdb
UART_proj/pro/db/UART_top.map_bb.logdb
UART_proj/pro/db/UART_top.pre_map.hdb
UART_proj/pro/db/UART_top.pti_db_list.ddb
UART_proj/pro/db/UART_top.root_partition.map.reg_db.cdb
UART_proj/pro/db/UART_top.routing.rdb
UART_proj/pro/db/UART_top.rtlv.hdb
UART_proj/pro/db/UART_top.rtlv_sg.cdb
UART_proj/pro/db/UART_top.rtlv_sg_swap.cdb
UART_proj/pro/db/UART_top.sgdiff.cdb
UART_proj/pro/db/UART_top.sgdiff.hdb
UART_proj/pro/db/UART_top.sld_design_entry.sci
UART_proj/pro/db/UART_top.sld_design_entry_dsc.sci
UART_proj/pro/db/UART_top.smart_action.txt
UART_proj/pro/db/UART_top.sta.qmsg
UART_proj/pro/db/UART_top.sta.rdb
UART_proj/pro/db/UART_top.sta_cmp.8_slow.tdb
UART_proj/pro/db/UART_top.syn_hier_info
UART_proj/pro/db/UART_top.tis_db_list.ddb
UART_proj/pro/db/UART_top.tmw_info
UART_proj/pro/db/UART_top.vpr.ammdb
UART_proj/pro/greybox_tmp/cbx_args.txt
UART_proj/pro/incremental_db/compiled_partitions/UART_top.db_info
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.ammdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.cdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.dfp
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.hdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.kpt
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.logdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.cmp.rcfdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.cdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.dpi
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.hbdb.cdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.hbdb.hb_info
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.hbdb.hdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.hbdb.sig
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.hdb
UART_proj/pro/incremental_db/compiled_partitions/UART_top.root_partition.map.kpt
UART_proj/pro/incremental_db/README
UART_proj/pro/pll_1.ppf
UART_proj/pro/pll_1.qip
UART_proj/pro/pll_1.v
UART_proj/pro/pll_1_bb.v
UART_proj/pro/UART_top.asm.rpt
UART_proj/pro/UART_top.done
UART_proj/pro/UART_top.dpf
UART_proj/pro/UART_top.fit.rpt
UART_proj/pro/UART_top.fit.smsg
UART_proj/pro/UART_top.fit.summary
UART_proj/pro/UART_top.flow.rpt
UART_proj/pro/UART_top.jdi
UART_proj/pro/UART_top.map.rpt
UART_proj/pro/UART_top.map.smsg
UART_proj/pro/UART_top.map.summary
UART_proj/pro/UART_top.pin
UART_proj/pro/UART_top.pof
UART_proj/pro/UART_top.qpf
UART_proj/pro/UART_top.qsf
UART_proj/pro/UART_top.qsf.bak
UART_proj/pro/UART_top.qws
UART_proj/pro/UART_top.sdc
UART_proj/pro/UART_top.sof
UART_proj/pro/UART_top.sta.rpt
UART_proj/pro/UART_top.sta.summary
UART_proj/pro/UART_top_assignment_defaults.qdf
UART_proj/sim/vsim.wlf
UART_proj/sim/wave.do
UART_proj/sim/wlftnm88qt
UART_proj/sim/wlftvv3ikx
UART_proj/sim/work/data_generate/verilog.asm
UART_proj/sim/work/data_generate/verilog.rw
UART_proj/sim/work/data_generate/_primary.dat
UART_proj/sim/work/data_generate/_primary.dbs
UART_proj/sim/work/data_generate/_primary.vhd
UART_proj/sim/work/tb_@u@a@r@t_top/verilog.asm
UART_proj/sim/work/tb_@u@a@r@t_top/verilog.rw
UART_proj/sim/work/tb_@u@a@r@t_top/_primary.dat
UART

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