文件名称:test_uart
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- 上传时间:2015-07-30
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文件大小:359.51kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
verilog 编写的串口发送和接收模块,能够设定停止位和校验位,并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test_uart/my_uart_rx.v
test_uart/my_uart_top.v
test_uart/my_uart_tx.v
test_uart/Readme.txt
test_uart/speed_select.v
test_uart/speed_select.v.bak
test_uart/tb_uart.v
test_uart/tb_uart.v.bak
test_uart/test_uart.cr.mti
test_uart/test_uart.mpf
test_uart/vsim.wlf
test_uart/work/my_uart_rx/verilog.prw
test_uart/work/my_uart_rx/verilog.psm
test_uart/work/my_uart_rx/_primary.dat
test_uart/work/my_uart_rx/_primary.dbs
test_uart/work/my_uart_rx/_primary.vhd
test_uart/work/my_uart_top/verilog.prw
test_uart/work/my_uart_top/verilog.psm
test_uart/work/my_uart_top/_primary.dat
test_uart/work/my_uart_top/_primary.dbs
test_uart/work/my_uart_top/_primary.vhd
test_uart/work/my_uart_tx/verilog.prw
test_uart/work/my_uart_tx/verilog.psm
test_uart/work/my_uart_tx/_primary.dat
test_uart/work/my_uart_tx/_primary.dbs
test_uart/work/my_uart_tx/_primary.vhd
test_uart/work/speed_select/verilog.prw
test_uart/work/speed_select/verilog.psm
test_uart/work/speed_select/_primary.dat
test_uart/work/speed_select/_primary.dbs
test_uart/work/speed_select/_primary.vhd
test_uart/work/tb_uart/verilog.prw
test_uart/work/tb_uart/verilog.psm
test_uart/work/tb_uart/_primary.dat
test_uart/work/tb_uart/_primary.dbs
test_uart/work/tb_uart/_primary.vhd
test_uart/work/_info
test_uart/work/_temp/vlog02kg5n
test_uart/work/_temp/vlogdhw9w9
test_uart/work/_temp/vlogf11vkk
test_uart/work/_temp/vlogi1mxk6
test_uart/work/_temp/vlogwh0wzx
test_uart/work/_vmake
test_uart/work/my_uart_rx
test_uart/work/my_uart_top
test_uart/work/my_uart_tx
test_uart/work/speed_select
test_uart/work/tb_uart
test_uart/work/_temp
test_uart/work
test_uart
test_uart/my_uart_top.v
test_uart/my_uart_tx.v
test_uart/Readme.txt
test_uart/speed_select.v
test_uart/speed_select.v.bak
test_uart/tb_uart.v
test_uart/tb_uart.v.bak
test_uart/test_uart.cr.mti
test_uart/test_uart.mpf
test_uart/vsim.wlf
test_uart/work/my_uart_rx/verilog.prw
test_uart/work/my_uart_rx/verilog.psm
test_uart/work/my_uart_rx/_primary.dat
test_uart/work/my_uart_rx/_primary.dbs
test_uart/work/my_uart_rx/_primary.vhd
test_uart/work/my_uart_top/verilog.prw
test_uart/work/my_uart_top/verilog.psm
test_uart/work/my_uart_top/_primary.dat
test_uart/work/my_uart_top/_primary.dbs
test_uart/work/my_uart_top/_primary.vhd
test_uart/work/my_uart_tx/verilog.prw
test_uart/work/my_uart_tx/verilog.psm
test_uart/work/my_uart_tx/_primary.dat
test_uart/work/my_uart_tx/_primary.dbs
test_uart/work/my_uart_tx/_primary.vhd
test_uart/work/speed_select/verilog.prw
test_uart/work/speed_select/verilog.psm
test_uart/work/speed_select/_primary.dat
test_uart/work/speed_select/_primary.dbs
test_uart/work/speed_select/_primary.vhd
test_uart/work/tb_uart/verilog.prw
test_uart/work/tb_uart/verilog.psm
test_uart/work/tb_uart/_primary.dat
test_uart/work/tb_uart/_primary.dbs
test_uart/work/tb_uart/_primary.vhd
test_uart/work/_info
test_uart/work/_temp/vlog02kg5n
test_uart/work/_temp/vlogdhw9w9
test_uart/work/_temp/vlogf11vkk
test_uart/work/_temp/vlogi1mxk6
test_uart/work/_temp/vlogwh0wzx
test_uart/work/_vmake
test_uart/work/my_uart_rx
test_uart/work/my_uart_top
test_uart/work/my_uart_tx
test_uart/work/speed_select
test_uart/work/tb_uart
test_uart/work/_temp
test_uart/work
test_uart
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