文件名称:pc_fpga_com_latest.tar
-
所属分类:
- 标签属性:
- 上传时间:2015-08-06
-
文件大小:183.48kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
Example Project on how to communicate PC to FPGA using UDP/TCP packets-Example Project on how to communicate PC to FPGA using UDP/TCP packets
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pc_fpga_com/
pc_fpga_com/tags/
pc_fpga_com/branches/
pc_fpga_com/trunk/
pc_fpga_com/trunk/README.txt
pc_fpga_com/trunk/PAPER/
pc_fpga_com/trunk/PAPER/pc_fpga_com.pdf
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_8b_wren.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/UDP_IP_Core.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/MATCH_CMD.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPv4_PACKET_RECEIVER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/OVERRIDE_LUT_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_TRANS.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_LUT_INDEXER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_RECEIV.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/CONFIG_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/PACKET_RECEIVER_FSM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/FLEX_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/TARGET_EOF.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_PACKET_TRANSMITTER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_16B_WREN.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_8b_wren.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/UDP_IP_Core.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/MATCH_CMD.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPv4_PACKET_RECEIVER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/OVERRIDE_LUT_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_TRANS.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_LUT_INDEXER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_RECEIV.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/CONFIG_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/PACKET_RECEIVER_FSM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/FLEX_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/TARGET_EOF.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_PACKET_TRANSMITTER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_16B_WREN.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FPGA2PC.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC2FPGA.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MATCH_CMD.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FSM_SEL_HEADER.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/DATA_OUT_MUX.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC_COM.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MODE_SEL_REGISTER.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/D_TYPE_LEN_CNTRL.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.h
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/build.sh
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/testcase1.cpp
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.h
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/README
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.c
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.cpp
pc_fpga_com/tags/
pc_fpga_com/branches/
pc_fpga_com/trunk/
pc_fpga_com/trunk/README.txt
pc_fpga_com/trunk/PAPER/
pc_fpga_com/trunk/PAPER/pc_fpga_com.pdf
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_8b_wren.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/UDP_IP_Core.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/MATCH_CMD.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPv4_PACKET_RECEIVER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/OVERRIDE_LUT_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_TRANS.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_LUT_INDEXER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_RECEIV.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/CONFIG_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/PACKET_RECEIVER_FSM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/FLEX_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/TARGET_EOF.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_PACKET_TRANSMITTER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_16B_WREN.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_8b_wren.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/UDP_IP_Core.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/MATCH_CMD.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPv4_PACKET_RECEIVER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/OVERRIDE_LUT_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_TRANS.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_LUT_INDEXER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_RECEIV.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/CONFIG_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/PACKET_RECEIVER_FSM.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/FLEX_CONTROL.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.xco
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/TARGET_EOF.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.ngc
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_PACKET_TRANSMITTER.vhd
pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_16B_WREN.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FPGA2PC.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC2FPGA.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MATCH_CMD.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FSM_SEL_HEADER.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/DATA_OUT_MUX.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC_COM.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MODE_SEL_REGISTER.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/D_TYPE_LEN_CNTRL.vhd
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.h
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/build.sh
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/testcase1.cpp
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.h
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/README
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.c
pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.cpp
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.