文件名称:sin_quartus9.0
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- 上传时间:2015-08-10
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文件大小:4.04mb
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用Verilog实现不同相位的正弦波波形输出,使用到ROM查表方式,对不同相位的地址进行合成后查表得到不同相位的正弦波。-Implementation of Sine wave output with different phase.
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下载文件列表
sin2/
sin2/clk_54k.v
sin2/db/
sin2/db/altsyncram_au81.tdf
sin2/db/logic_util_heursitic.dat
sin2/db/prev_cmp_sin2.qmsg
sin2/db/sin2.(0).cnf.cdb
sin2/db/sin2.(0).cnf.hdb
sin2/db/sin2.(1).cnf.cdb
sin2/db/sin2.(1).cnf.hdb
sin2/db/sin2.(10).cnf.cdb
sin2/db/sin2.(10).cnf.hdb
sin2/db/sin2.(2).cnf.cdb
sin2/db/sin2.(2).cnf.hdb
sin2/db/sin2.(3).cnf.cdb
sin2/db/sin2.(3).cnf.hdb
sin2/db/sin2.(4).cnf.cdb
sin2/db/sin2.(4).cnf.hdb
sin2/db/sin2.(5).cnf.cdb
sin2/db/sin2.(5).cnf.hdb
sin2/db/sin2.(6).cnf.cdb
sin2/db/sin2.(6).cnf.hdb
sin2/db/sin2.(7).cnf.cdb
sin2/db/sin2.(7).cnf.hdb
sin2/db/sin2.(8).cnf.cdb
sin2/db/sin2.(8).cnf.hdb
sin2/db/sin2.(9).cnf.cdb
sin2/db/sin2.(9).cnf.hdb
sin2/db/sin2.amm.cdb
sin2/db/sin2.asm.qmsg
sin2/db/sin2.asm.rdb
sin2/db/sin2.asm_labs.ddb
sin2/db/sin2.cbx.xml
sin2/db/sin2.cmp.bpm
sin2/db/sin2.cmp.cdb
sin2/db/sin2.cmp.hdb
sin2/db/sin2.cmp.kpt
sin2/db/sin2.cmp.logdb
sin2/db/sin2.cmp.rdb
sin2/db/sin2.cmp_merge.kpt
sin2/db/sin2.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
sin2/db/sin2.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
sin2/db/sin2.db_info
sin2/db/sin2.eda.qmsg
sin2/db/sin2.fit.qmsg
sin2/db/sin2.hier_info
sin2/db/sin2.hif
sin2/db/sin2.idb.cdb
sin2/db/sin2.lpc.html
sin2/db/sin2.lpc.rdb
sin2/db/sin2.lpc.txt
sin2/db/sin2.map.bpm
sin2/db/sin2.map.cdb
sin2/db/sin2.map.hdb
sin2/db/sin2.map.kpt
sin2/db/sin2.map.logdb
sin2/db/sin2.map.qmsg
sin2/db/sin2.map_bb.cdb
sin2/db/sin2.map_bb.hdb
sin2/db/sin2.map_bb.logdb
sin2/db/sin2.pre_map.cdb
sin2/db/sin2.pre_map.hdb
sin2/db/sin2.rtlv.hdb
sin2/db/sin2.rtlv_sg.cdb
sin2/db/sin2.rtlv_sg_swap.cdb
sin2/db/sin2.sgdiff.cdb
sin2/db/sin2.sgdiff.hdb
sin2/db/sin2.sld_design_entry.sci
sin2/db/sin2.sld_design_entry_dsc.sci
sin2/db/sin2.smart_action.txt
sin2/db/sin2.sta.qmsg
sin2/db/sin2.sta.rdb
sin2/db/sin2.sta_cmp.8_slow_1200mv_85c.tdb
sin2/db/sin2.syn_hier_info
sin2/db/sin2.tiscmp.fastest_slow_1200mv_0c.ddb
sin2/db/sin2.tiscmp.fastest_slow_1200mv_85c.ddb
sin2/db/sin2.tiscmp.fast_1200mv_0c.ddb
sin2/db/sin2.tiscmp.slow_1200mv_0c.ddb
sin2/db/sin2.tiscmp.slow_1200mv_85c.ddb
sin2/db/sin2.tis_db_list.ddb
sin2/db/sin2.tmw_info
sin2/dizhihecheng.v
sin2/greybox_tmp/
sin2/greybox_tmp/cbx_args.txt
sin2/incremental_db/
sin2/incremental_db/compiled_partitions/
sin2/incremental_db/compiled_partitions/sin2.db_info
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.dfp
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.kpt
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.logdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.rcfdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.dpi
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.hb_info
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.sig
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.kpt
sin2/incremental_db/README
sin2/rom.bsf
sin2/rom.inc
sin2/rom.mif
sin2/rom.qip
sin2/rom.v
sin2/rom_bb.v
sin2/rom_inst.v
sin2/shujufenli.v
sin2/simulation/
sin2/simulation/modelsim/
sin2/simulation/modelsim/modelsim.ini
sin2/simulation/modelsim/msim_transcript
sin2/simulation/modelsim/rom.mif
sin2/simulation/modelsim/rom.ver
sin2/simulation/modelsim/rtl_work/
sin2/simulation/modelsim/rtl_work/clk_54k/
sin2/simulation/modelsim/rtl_work/clk_54k/_primary.dat
sin2/simulation/modelsim/rtl_work/clk_54k/_primary.vhd
sin2/simulation/modelsim/rtl_work/dizhihecheng/
sin2/simulation/modelsim/rtl_work/dizhihecheng/_primary.dat
sin2/simulation/modelsim/rtl_work/dizhihecheng/_primary.vhd
sin2/simulation/modelsim/rtl_work/rom/
sin2/simulation/modelsim/rtl_work/rom/_primary.dat
sin2/simulation/modelsim/rtl_work/rom/_primary.vhd
sin2/simulation/modelsim/rtl_work/shujufenli/
sin2/simulation/modelsim/rtl_work/shujufenli/_primary.dat
sin2/simulation/modelsim/rtl_work/shujufenli/_primary.vhd
sin2/simulation/modelsim/rtl_work/sin2/
sin2/simulation/modelsim/rtl_work/sin2/_primary.dat
sin2/simulation/modelsim/rtl_work/sin2/_primary.vhd
sin2/simulation/modelsim/rtl_work/test_tb1/
sin2/simulation/modelsim/rtl_work/test_tb1/_primary.dat
sin2/simulation/modelsim/rtl_work/test_tb1/_primary.vhd
sin2/simulation/modelsim/rtl_work/_info
sin2/simulation/modelsim/rtl_work/_opt/
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_lnsim_ver__info
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s_fast.asm
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s_fast.dt2
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n_fast.asm
sin2/simulation/modelsim/rtl_work/_opt
sin2/clk_54k.v
sin2/db/
sin2/db/altsyncram_au81.tdf
sin2/db/logic_util_heursitic.dat
sin2/db/prev_cmp_sin2.qmsg
sin2/db/sin2.(0).cnf.cdb
sin2/db/sin2.(0).cnf.hdb
sin2/db/sin2.(1).cnf.cdb
sin2/db/sin2.(1).cnf.hdb
sin2/db/sin2.(10).cnf.cdb
sin2/db/sin2.(10).cnf.hdb
sin2/db/sin2.(2).cnf.cdb
sin2/db/sin2.(2).cnf.hdb
sin2/db/sin2.(3).cnf.cdb
sin2/db/sin2.(3).cnf.hdb
sin2/db/sin2.(4).cnf.cdb
sin2/db/sin2.(4).cnf.hdb
sin2/db/sin2.(5).cnf.cdb
sin2/db/sin2.(5).cnf.hdb
sin2/db/sin2.(6).cnf.cdb
sin2/db/sin2.(6).cnf.hdb
sin2/db/sin2.(7).cnf.cdb
sin2/db/sin2.(7).cnf.hdb
sin2/db/sin2.(8).cnf.cdb
sin2/db/sin2.(8).cnf.hdb
sin2/db/sin2.(9).cnf.cdb
sin2/db/sin2.(9).cnf.hdb
sin2/db/sin2.amm.cdb
sin2/db/sin2.asm.qmsg
sin2/db/sin2.asm.rdb
sin2/db/sin2.asm_labs.ddb
sin2/db/sin2.cbx.xml
sin2/db/sin2.cmp.bpm
sin2/db/sin2.cmp.cdb
sin2/db/sin2.cmp.hdb
sin2/db/sin2.cmp.kpt
sin2/db/sin2.cmp.logdb
sin2/db/sin2.cmp.rdb
sin2/db/sin2.cmp_merge.kpt
sin2/db/sin2.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
sin2/db/sin2.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
sin2/db/sin2.db_info
sin2/db/sin2.eda.qmsg
sin2/db/sin2.fit.qmsg
sin2/db/sin2.hier_info
sin2/db/sin2.hif
sin2/db/sin2.idb.cdb
sin2/db/sin2.lpc.html
sin2/db/sin2.lpc.rdb
sin2/db/sin2.lpc.txt
sin2/db/sin2.map.bpm
sin2/db/sin2.map.cdb
sin2/db/sin2.map.hdb
sin2/db/sin2.map.kpt
sin2/db/sin2.map.logdb
sin2/db/sin2.map.qmsg
sin2/db/sin2.map_bb.cdb
sin2/db/sin2.map_bb.hdb
sin2/db/sin2.map_bb.logdb
sin2/db/sin2.pre_map.cdb
sin2/db/sin2.pre_map.hdb
sin2/db/sin2.rtlv.hdb
sin2/db/sin2.rtlv_sg.cdb
sin2/db/sin2.rtlv_sg_swap.cdb
sin2/db/sin2.sgdiff.cdb
sin2/db/sin2.sgdiff.hdb
sin2/db/sin2.sld_design_entry.sci
sin2/db/sin2.sld_design_entry_dsc.sci
sin2/db/sin2.smart_action.txt
sin2/db/sin2.sta.qmsg
sin2/db/sin2.sta.rdb
sin2/db/sin2.sta_cmp.8_slow_1200mv_85c.tdb
sin2/db/sin2.syn_hier_info
sin2/db/sin2.tiscmp.fastest_slow_1200mv_0c.ddb
sin2/db/sin2.tiscmp.fastest_slow_1200mv_85c.ddb
sin2/db/sin2.tiscmp.fast_1200mv_0c.ddb
sin2/db/sin2.tiscmp.slow_1200mv_0c.ddb
sin2/db/sin2.tiscmp.slow_1200mv_85c.ddb
sin2/db/sin2.tis_db_list.ddb
sin2/db/sin2.tmw_info
sin2/dizhihecheng.v
sin2/greybox_tmp/
sin2/greybox_tmp/cbx_args.txt
sin2/incremental_db/
sin2/incremental_db/compiled_partitions/
sin2/incremental_db/compiled_partitions/sin2.db_info
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.dfp
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.kpt
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.logdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.cmp.rcfdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.dpi
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.cdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.hb_info
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hbdb.sig
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.hdb
sin2/incremental_db/compiled_partitions/sin2.root_partition.map.kpt
sin2/incremental_db/README
sin2/rom.bsf
sin2/rom.inc
sin2/rom.mif
sin2/rom.qip
sin2/rom.v
sin2/rom_bb.v
sin2/rom_inst.v
sin2/shujufenli.v
sin2/simulation/
sin2/simulation/modelsim/
sin2/simulation/modelsim/modelsim.ini
sin2/simulation/modelsim/msim_transcript
sin2/simulation/modelsim/rom.mif
sin2/simulation/modelsim/rom.ver
sin2/simulation/modelsim/rtl_work/
sin2/simulation/modelsim/rtl_work/clk_54k/
sin2/simulation/modelsim/rtl_work/clk_54k/_primary.dat
sin2/simulation/modelsim/rtl_work/clk_54k/_primary.vhd
sin2/simulation/modelsim/rtl_work/dizhihecheng/
sin2/simulation/modelsim/rtl_work/dizhihecheng/_primary.dat
sin2/simulation/modelsim/rtl_work/dizhihecheng/_primary.vhd
sin2/simulation/modelsim/rtl_work/rom/
sin2/simulation/modelsim/rtl_work/rom/_primary.dat
sin2/simulation/modelsim/rtl_work/rom/_primary.vhd
sin2/simulation/modelsim/rtl_work/shujufenli/
sin2/simulation/modelsim/rtl_work/shujufenli/_primary.dat
sin2/simulation/modelsim/rtl_work/shujufenli/_primary.vhd
sin2/simulation/modelsim/rtl_work/sin2/
sin2/simulation/modelsim/rtl_work/sin2/_primary.dat
sin2/simulation/modelsim/rtl_work/sin2/_primary.vhd
sin2/simulation/modelsim/rtl_work/test_tb1/
sin2/simulation/modelsim/rtl_work/test_tb1/_primary.dat
sin2/simulation/modelsim/rtl_work/test_tb1/_primary.vhd
sin2/simulation/modelsim/rtl_work/_info
sin2/simulation/modelsim/rtl_work/_opt/
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_lnsim_ver__info
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s_fast.asm
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s_fast.dt2
sin2/simulation/modelsim/rtl_work/_opt/._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n_fast.asm
sin2/simulation/modelsim/rtl_work/_opt
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