文件名称:7495
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shift register 7495 four d flip flop 5 mux
5495A/DM7495
4-Bit Parallel Access Shift Registers
General Descr iption
These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accomplished
on the high-to-low transition of clock 2 when th-shift register 7495 four d flip flop 5 mux
5495A/DM7495
4-Bit Parallel Access Shift Registers
General Descr iption
These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accomplished
on the high-to-low transition of clock 2 when th
5495A/DM7495
4-Bit Parallel Access Shift Registers
General Descr iption
These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accomplished
on the high-to-low transition of clock 2 when th-shift register 7495 four d flip flop 5 mux
5495A/DM7495
4-Bit Parallel Access Shift Registers
General Descr iption
These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accomplished
on the high-to-low transition of clock 2 when th
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下载文件列表
7495/.lso
7495/7495.ise
7495/7495.ise_ISE_Backup
7495/7495.restore
7495/dff.vhd
7495/isim/work/dff/behavioral.h
7495/isim/work/dff/mingw/behavioral.obj
7495/isim/work/hdllib.ref
7495/isim/work/hdpdeps.ref
7495/isim/work/mux/behavioral.h
7495/isim/work/mux/mingw/behavioral.obj
7495/isim/work/shift_reg/behavioral.h
7495/isim/work/shift_reg/mingw/behavioral.obj
7495/isim/work/sub00/vhpl00.vho
7495/isim/work/sub00/vhpl01.vho
7495/isim/work/sub00/vhpl02.vho
7495/isim/work/sub00/vhpl03.vho
7495/isim/work/sub00/vhpl04.vho
7495/isim/work/sub00/vhpl05.vho
7495/isim/work/sub00/vhpl06.vho
7495/isim/work/sub00/vhpl07.vho
7495/isim/work/test/mingw/testbench_arch.obj
7495/isim/work/test/testbench_arch.h
7495/isim/work/test/xsimtestbench_arch.cpp
7495/isim.cmd
7495/isim.hdlsourcefiles
7495/isim.log
7495/isim.tmp_save/_1
7495/isimwavedata.xwv
7495/mux.vhd
7495/pepExtractor.prj
7495/results.txt
7495/shift_reg.prj
7495/shift_reg.stx
7495/shift_reg.vhd
7495/shift_reg.xst
7495/shift_reg_summary.html
7495/shift_reg_vhdl.prj
7495/simulate_dofile.log
7495/simulate_dofile.log_back
7495/test.ant
7495/test.jhd
7495/test.tbw
7495/test.vhw
7495/test.xwv
7495/test.xwv_bak
7495/test_beh.prj
7495/test_bencher.prj
7495/test_isim_beh.exe
7495/test_isim_beh.wfs
7495/xilinxsim.ini
7495/xst/work/hdllib.ref
7495/xst/work/hdpdeps.ref
7495/xst/work/sub00/vhpl00.vho
7495/xst/work/sub00/vhpl01.vho
7495/xst/work/sub00/vhpl02.vho
7495/xst/work/sub00/vhpl03.vho
7495/xst/work/sub00/vhpl04.vho
7495/xst/work/sub00/vhpl05.vho
7495/_xmsgs/fuse.xmsgs
7495/_xmsgs/vhpcomp.xmsgs
7495/_xmsgs/xst.xmsgs
7495/__ISE_repository_7495.ise_.lock
7495/isim/work/dff/mingw
7495/isim/work/mux/mingw
7495/isim/work/shift_reg/mingw
7495/isim/work/test/mingw
7495/isim/work/dff
7495/isim/work/mux
7495/isim/work/shift_reg
7495/isim/work/sub00
7495/isim/work/test
7495/xst/work/sub00
7495/isim/file graph
7495/isim/work
7495/xst/file graph
7495/xst/projnav.tmp
7495/xst/work
7495/isim
7495/isim.tmp_save
7495/xst
7495/_xmsgs
7495
7495/7495.ise
7495/7495.ise_ISE_Backup
7495/7495.restore
7495/dff.vhd
7495/isim/work/dff/behavioral.h
7495/isim/work/dff/mingw/behavioral.obj
7495/isim/work/hdllib.ref
7495/isim/work/hdpdeps.ref
7495/isim/work/mux/behavioral.h
7495/isim/work/mux/mingw/behavioral.obj
7495/isim/work/shift_reg/behavioral.h
7495/isim/work/shift_reg/mingw/behavioral.obj
7495/isim/work/sub00/vhpl00.vho
7495/isim/work/sub00/vhpl01.vho
7495/isim/work/sub00/vhpl02.vho
7495/isim/work/sub00/vhpl03.vho
7495/isim/work/sub00/vhpl04.vho
7495/isim/work/sub00/vhpl05.vho
7495/isim/work/sub00/vhpl06.vho
7495/isim/work/sub00/vhpl07.vho
7495/isim/work/test/mingw/testbench_arch.obj
7495/isim/work/test/testbench_arch.h
7495/isim/work/test/xsimtestbench_arch.cpp
7495/isim.cmd
7495/isim.hdlsourcefiles
7495/isim.log
7495/isim.tmp_save/_1
7495/isimwavedata.xwv
7495/mux.vhd
7495/pepExtractor.prj
7495/results.txt
7495/shift_reg.prj
7495/shift_reg.stx
7495/shift_reg.vhd
7495/shift_reg.xst
7495/shift_reg_summary.html
7495/shift_reg_vhdl.prj
7495/simulate_dofile.log
7495/simulate_dofile.log_back
7495/test.ant
7495/test.jhd
7495/test.tbw
7495/test.vhw
7495/test.xwv
7495/test.xwv_bak
7495/test_beh.prj
7495/test_bencher.prj
7495/test_isim_beh.exe
7495/test_isim_beh.wfs
7495/xilinxsim.ini
7495/xst/work/hdllib.ref
7495/xst/work/hdpdeps.ref
7495/xst/work/sub00/vhpl00.vho
7495/xst/work/sub00/vhpl01.vho
7495/xst/work/sub00/vhpl02.vho
7495/xst/work/sub00/vhpl03.vho
7495/xst/work/sub00/vhpl04.vho
7495/xst/work/sub00/vhpl05.vho
7495/_xmsgs/fuse.xmsgs
7495/_xmsgs/vhpcomp.xmsgs
7495/_xmsgs/xst.xmsgs
7495/__ISE_repository_7495.ise_.lock
7495/isim/work/dff/mingw
7495/isim/work/mux/mingw
7495/isim/work/shift_reg/mingw
7495/isim/work/test/mingw
7495/isim/work/dff
7495/isim/work/mux
7495/isim/work/shift_reg
7495/isim/work/sub00
7495/isim/work/test
7495/xst/work/sub00
7495/isim/file graph
7495/isim/work
7495/xst/file graph
7495/xst/projnav.tmp
7495/xst/work
7495/isim
7495/isim.tmp_save
7495/xst
7495/_xmsgs
7495
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