Oscilloscope/readme.txt
Oscilloscope/Ready_for_download/B3_OSC_download.bit
Oscilloscope/Src/Constraint/oscilloscope.xdc
Oscilloscope/Src/HDL_source/char_rom_mapping.v
Oscilloscope/Src/HDL_source/clock/clock.xci
Oscilloscope/Src/HDL_source/clock_control.v
Oscilloscope/Src/HDL_source/debounce_0/debounce_0.dcp
Oscilloscope/Src/HDL_source/debounce_0/debounce_0.veo
Oscilloscope/Src/HDL_source/debounce_0/debounce_0.xci
Oscilloscope/Src/HDL_source/debounce_0/debounce_0.xml
Oscilloscope/Src/HDL_source/debounce_0/debounce_0_funcsim.v
Oscilloscope/Src/HDL_source/debounce_0/debounce_0_funcsim.vhdl
Oscilloscope/Src/HDL_source/debounce_0/debounce_0_stub.v
Oscilloscope/Src/HDL_source/debounce_0/debounce_0_stub.vhdl
Oscilloscope/Src/HDL_source/debounce_0/sim/debounce_0.v
Oscilloscope/Src/HDL_source/debounce_0/sim_1/new/debounce_tb.v
Oscilloscope/Src/HDL_source/debounce_0/sources_1/new/debounce.v
Oscilloscope/Src/HDL_source/debounce_0/synth/debounce_0.v
Oscilloscope/Src/HDL_source/Fre_Calculate.v
Oscilloscope/Src/HDL_source/Fre_Vopp_mapping_rom.v
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_debounce_1.0/component.xml
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_debounce_1.0/sim_1/new/debounce_tb.v
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_debounce_1.0/sources_1/new/debounce.v
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_debounce_1.0/xgui/debounce_v1_0.tcl
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_debounce_1.0.zip
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_vga_1.0/component.xml
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_vga_1.0/vga.v
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_vga_1.0/xgui/vga_v1_0.tcl
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_vga_1.0.zip
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_xadc_1.0/component.xml
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_xadc_1.0/ip/xadc_wiz_0/xadc_wiz_0.xci
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_xadc_1.0/new/xadc.v
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_xadc_1.0/xgui/xadc_v1_0.tcl
Oscilloscope/Src/HDL_source/IP_Catalog/XUP_xadc_1.0.zip
Oscilloscope/Src/HDL_source/OSC_top.v
Oscilloscope/Src/HDL_source/trigger.v
Oscilloscope/Src/HDL_source/vga_0/sim/vga_0.v
Oscilloscope/Src/HDL_source/vga_0/synth/vga_0.v
Oscilloscope/Src/HDL_source/vga_0/vga.v
Oscilloscope/Src/HDL_source/vga_0/vga_0.dcp
Oscilloscope/Src/HDL_source/vga_0/vga_0.veo
Oscilloscope/Src/HDL_source/vga_0/vga_0.xci
Oscilloscope/Src/HDL_source/vga_0/vga_0.xml
Oscilloscope/Src/HDL_source/vga_0/vga_0_funcsim.v
Oscilloscope/Src/HDL_source/vga_0/vga_0_funcsim.vhdl
Oscilloscope/Src/HDL_source/vga_0/vga_0_stub.v
Oscilloscope/Src/HDL_source/vga_0/vga_0_stub.vhdl
Oscilloscope/Src/HDL_source/vga_initials.v
Oscilloscope/Src/HDL_source/waveform_mapping_rom.v
Oscilloscope/Src/HDL_source/waveform_ram.v
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0/simulation/functional/design.txt
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0/simulation/timing/design.txt
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0.v
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0.xci
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0.xdc
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0.xml
Oscilloscope/Src/HDL_source/xadc_0/ip/xadc_wiz_0/xadc_wiz_0_ooc.xdc
Oscilloscope/Src/HDL_source/xadc_0/new/xadc.v
Oscilloscope/Src/HDL_source/xadc_0/sim/xadc_0.v
Oscilloscope/Src/HDL_source/xadc_0/synth/xadc_0.v
Oscilloscope/Src/HDL_source/xadc_0/xadc_0.dcp
Oscilloscope/Src/HDL_source/xadc_0/xadc_0.veo
Oscilloscope/Src/HDL_source/xadc_0/xadc_0.xci
Oscilloscope/Src/HDL_source/xadc_0/xadc_0.xml
Oscilloscope/Src/HDL_source/xadc_0/xadc_0_funcsim.v
Oscilloscope/Src/HDL_source/xadc_0/xadc_0_funcsim.vhdl
Oscilloscope/Src/HDL_source/xadc_0/xadc_0_stub.v
Oscilloscope/Src/HDL_source/xadc_0/xadc_0_stub.vhdl
Oscilloscope/Src/prj/Oscilloscope.cache/wt/java_command_handlers.wdf
Oscilloscope/Src/prj/Oscilloscope.cache/wt/synthesis.wdf
Oscilloscope/Src/prj/Oscilloscope.cache/wt/synthesis_details.wdf
Oscilloscope/Src/prj/Oscilloscope.cache/wt/webtalk_pa.xml
Oscilloscope/Src/prj/Oscilloscope.runs/.jobs/vrs_config_1.xml
Oscilloscope/Src/prj/Oscilloscope.runs/.jobs/vrs_config_2.xml
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/.vivado.begin.rst
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/.vivado.end.rst
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/.Vivado_Synthesis.queue.rst
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/.Xil/clock_propImpl.xdc
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/clock.dcp
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/clock.tcl
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/clock.vds
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/clock_utilization_synth.pb
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/clock_utilization_synth.rpt
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/dont_touch.xdc
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/gen_run.xml
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/htr.txt
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/ISEWrap.js
Oscilloscope/Src/prj/Oscilloscope.runs/clock_synth_1/ISEWrap.sh
Oscilloscope/