文件名称:wb_uart_latest.tar
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实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。
请找到有关于UART内核的文档。
该接口是现在有8位Wishbone总线兼容。
随着GHDL模拟器只需运行：
./ghdl_uart.bat
使用任何其他模拟器，开始模拟以下perl脚本必须运行之前：
uart_test_stim.pl> FILENAME.TXT
其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。
正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.
Please find there the documentation regarding the Uart core.
The interface is now compatible with a 8-bit WishBone bus.
With GHDL simulator simply run:
./ghdl_uart.bat
Using any other simulator, before starting the simulation the following perl scr ipt must be run:
uart_test_stim.pl > filename.txt
where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd.
A correct simulation should exit with an assertion message simulation END .
请找到有关于UART内核的文档。
该接口是现在有8位Wishbone总线兼容。
随着GHDL模拟器只需运行：
./ghdl_uart.bat
使用任何其他模拟器，开始模拟以下perl脚本必须运行之前：
uart_test_stim.pl> FILENAME.TXT
其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。
正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.
Please find there the documentation regarding the Uart core.
The interface is now compatible with a 8-bit WishBone bus.
With GHDL simulator simply run:
./ghdl_uart.bat
Using any other simulator, before starting the simulation the following perl scr ipt must be run:
uart_test_stim.pl > filename.txt
where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd.
A correct simulation should exit with an assertion message simulation END .
(系统自动生成,下载前可以参看下载内容)
下载文件列表
wb_uart/
wb_uart/tags/
wb_uart/branches/
wb_uart/trunk/
wb_uart/trunk/ghdl_uart.bat
wb_uart/trunk/src/
wb_uart/trunk/src/wb8_uart_package.vhd
wb_uart/trunk/src/slib_clock_div.vhd
wb_uart/trunk/src/slib_input_filter.vhd
wb_uart/trunk/src/uart_receiver.vhd
wb_uart/trunk/src/wb8_uart_16750.vhd
wb_uart/trunk/src/slib_mv_filter.vhd
wb_uart/trunk/src/slib_counter.vhd
wb_uart/trunk/src/slib_edge_detect.vhd
wb_uart/trunk/src/uart_transmitter.vhd
wb_uart/trunk/src/uart_baudgen.vhd
wb_uart/trunk/src/slib_fifo.vhd
wb_uart/trunk/src/uart_interrupt.vhd
wb_uart/trunk/src/wb8_uart_transactor.vhd
wb_uart/trunk/src/txt_util.vhd
wb_uart/trunk/src/slib_input_sync.vhd
wb_uart/tags/
wb_uart/branches/
wb_uart/trunk/
wb_uart/trunk/ghdl_uart.bat
wb_uart/trunk/src/
wb_uart/trunk/src/wb8_uart_package.vhd
wb_uart/trunk/src/slib_clock_div.vhd
wb_uart/trunk/src/slib_input_filter.vhd
wb_uart/trunk/src/uart_receiver.vhd
wb_uart/trunk/src/wb8_uart_16750.vhd
wb_uart/trunk/src/slib_mv_filter.vhd
wb_uart/trunk/src/slib_counter.vhd
wb_uart/trunk/src/slib_edge_detect.vhd
wb_uart/trunk/src/uart_transmitter.vhd
wb_uart/trunk/src/uart_baudgen.vhd
wb_uart/trunk/src/slib_fifo.vhd
wb_uart/trunk/src/uart_interrupt.vhd
wb_uart/trunk/src/wb8_uart_transactor.vhd
wb_uart/trunk/src/txt_util.vhd
wb_uart/trunk/src/slib_input_sync.vhd
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