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文件名称:SRIO-phy-code

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-09-21
  • 文件大小：
    183.63kb
  • 已下载：
    2次
  • 提 供 者：
    小***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SRIO phy code/pcs code/srio_pcs_code/core/wl_fifo.v
SRIO phy code/pcs code/srio_pcs_code/core/wl_fpga_afifo_192x16.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_lane.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_scram.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_seed_adstract.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_seq_gen.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_sync_check.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_descram_xor.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_idle_gen.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_idle_gen_ctrl.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_idle_gen_lane.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_scram.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_scram_ctrl.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_scram_lane.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_d_scram_seq.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_rx.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_rx_bw.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_rx_destripe.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_rx_fifo.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx_bw.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx_ccs_index.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx_fifo.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx_flow_fifo.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_gi_tx_stripe.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_1x_mode_detect.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_1x_mode_detect_sub.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_deskew.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_deskew_2x.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_deskew_4x.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_deskew_adj.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_deskew_cal.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_idle_detect.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_lane_align.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_lane_align_state.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_lane_sync.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_lane_sync_lane.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_init_mode_sel.v
SRIO phy code/pcs code/srio_pcs_code/rtl/srio_pcs_status.v
SRIO phy code/receive and master/ctrl_pack_proc_4x.v
SRIO phy code/receive and master/ctrl_sym_proc_2x_4x.v
SRIO phy code/receive and master/pack_proc_2x.v
SRIO phy code/receive and master/srio_cs_crc13.v
SRIO phy code/receive and master/srio_cs_crc5.v
SRIO phy code/receive and master/srio_data_crc16.v
SRIO phy code/receive and master/srio_phy_buf_ctrl.v
SRIO phy code/receive and master/srio_phy_fifo_15x64.v
SRIO phy code/receive and master/srio_phy_fifo_6x64.v
SRIO phy code/receive and master/srio_phy_master_control.v
SRIO phy code/receive and master/srio_phy_ram_64x4096.v
SRIO phy code/receive and master/srio_phy_reg.v
SRIO phy code/receive and master/srio_phy_rx.v
SRIO phy code/srio_phy_top.v
SRIO phy code/transmit code/contrl_err_detect.v
SRIO phy code/transmit code/data_128_to_64_switch.v
SRIO phy code/transmit code/data_logic_analys.v
SRIO phy code/transmit code/ipcore/ram_128_to_64/greybox_tmp/cbx_args.txt
SRIO phy code/transmit code/ipcore/ram_128_to_64/ram_128_to_64.qip
SRIO phy code/transmit code/ipcore/ram_128_to_64/ram_128_to_64.v
SRIO phy code/transmit code/ipcore/ram_128_to_64/ram_128_to_64_bb.v
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/greybox_tmp/cbx_args.txt
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/ram_128_to_64_bb.qip
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/ram_dat_fifo_2240x64.qip
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/ram_dat_fifo_2240x64.v
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/ram_dat_fifo_2240x64_bb.v
SRIO phy code/transmit code/ipcore/ram_dat_fifo2240x64/ram_dat_fifo_2240x64_syn.v
SRIO phy code/transmit code/output_err_retry_fsm.v
SRIO phy code/transmit code/pack_contr_distr.v
SRIO phy code/transmit code/pack_tran_top.v
SRIO phy code/transmit code/retransmission/package_inf_control.v
SRIO phy code/transmit code/retransmission/package_inf_dram_19x256.v
SRIO phy code/transmit code/retransmission/package_pri_adr_dram_19x64.v
SRIO phy code/transmit code/retransmission/pack_tx_ctr_unit.v
SRIO phy code/transmit code/retransmission/tx_adr_fifo_6x64.v
SRIO phy code/transmit code/retransmission/tx_pack_rec_dram_24x64.v
SRIO phy code/transmit code/stype0_store.v
SRIO phy code/transmit code/stype1_gen.v
SRIO phy code/transmit code/stype_ctrl_fifo.v
SRIO phy code/transmit code/tb_pack_tran_top.v
SRIO phy code/transmit code/ipcore/ram_128_to_64/greybox_tmp
SR

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