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文件名称:can

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Windows] [程序]
  • 上传时间：
    2015-10-12
  • 文件大小：
    1.64mb
  • 已下载：
    1次
  • 提 供 者：
    新***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

can/
can/tags/
can/tags/asyst_2/
can/tags/asyst_2/rtl/
can/tags/asyst_2/rtl/verilog/
can/tags/asyst_2/rtl/verilog/can_acf.v
can/tags/asyst_2/rtl/verilog/can_bsp.v
can/tags/asyst_2/rtl/verilog/can_btl.v
can/tags/asyst_2/rtl/verilog/can_crc.v
can/tags/asyst_2/rtl/verilog/can_defines.v
can/tags/asyst_2/rtl/verilog/can_fifo.v
can/tags/asyst_2/rtl/verilog/can_ibo.v
can/tags/asyst_2/rtl/verilog/can_register.v
can/tags/asyst_2/rtl/verilog/can_register_asyn.v
can/tags/asyst_2/rtl/verilog/can_register_asyn_syn.v
can/tags/asyst_2/rtl/verilog/can_register_syn.v
can/tags/asyst_2/rtl/verilog/can_registers.v
can/tags/asyst_2/rtl/verilog/can_top.v
can/tags/asyst_3/
can/tags/asyst_3/rtl/
can/tags/asyst_3/rtl/verilog/
can/tags/asyst_3/rtl/verilog/can_acf.v
can/tags/asyst_3/rtl/verilog/can_bsp.v
can/tags/asyst_3/rtl/verilog/can_btl.v
can/tags/asyst_3/rtl/verilog/can_crc.v
can/tags/asyst_3/rtl/verilog/can_defines.v
can/tags/asyst_3/rtl/verilog/can_fifo.v
can/tags/asyst_3/rtl/verilog/can_ibo.v
can/tags/asyst_3/rtl/verilog/can_register.v
can/tags/asyst_3/rtl/verilog/can_register_asyn.v
can/tags/asyst_3/rtl/verilog/can_register_asyn_syn.v
can/tags/asyst_3/rtl/verilog/can_register_syn.v
can/tags/asyst_3/rtl/verilog/can_registers.v
can/tags/asyst_3/rtl/verilog/can_top.v
can/tags/branch-release-1-0/
can/tags/branch-release-1-0/syn/
can/tags/branch-release-1-0/syn/libero/
can/tags/branch-release-1-0/syn/libero/pinedit.gcf
can/tags/branch-release-1-0/syn/synplicity/
can/tags/branch-release-1-0/syn/synplicity/can.prj
can/tags/branch-release-1-0/syn/synplicity/rev_1/
can/tags/branch-release-1-0/syn/synplicity/rev_1/dir_keeper
can/tags/complete_1/
can/tags/complete_1/bench/
can/tags/complete_1/bench/verilog/
can/tags/complete_1/bench/verilog/can_testbench.v
can/tags/complete_1/bench/verilog/can_testbench_defines.v
can/tags/complete_1/bench/verilog/timescale.v
can/tags/complete_1/rtl/
can/tags/complete_1/rtl/verilog/
can/tags/complete_1/rtl/verilog/can_acf.v
can/tags/complete_1/rtl/verilog/can_bsp.v
can/tags/complete_1/rtl/verilog/can_btl.v
can/tags/complete_1/rtl/verilog/can_crc.v
can/tags/complete_1/rtl/verilog/can_defines.v
can/tags/complete_1/rtl/verilog/can_fifo.v
can/tags/complete_1/rtl/verilog/can_ibo.v
can/tags/complete_1/rtl/verilog/can_register.v
can/tags/complete_1/rtl/verilog/can_register_asyn.v
can/tags/complete_1/rtl/verilog/can_register_asyn_syn.v
can/tags/complete_1/rtl/verilog/can_register_syn.v
can/tags/complete_1/rtl/verilog/can_registers.v
can/tags/complete_1/rtl/verilog/can_top.v
can/tags/complete_1/sim/
can/tags/complete_1/sim/rtl_sim/
can/tags/complete_1/sim/rtl_sim/bin/
can/tags/complete_1/sim/rtl_sim/bin/INCA_libs/
can/tags/complete_1/sim/rtl_sim/bin/INCA_libs/worklib/
can/tags/complete_1/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
can/tags/complete_1/sim/rtl_sim/bin/cds.lib
can/tags/complete_1/sim/rtl_sim/bin/hdl.var
can/tags/complete_1/sim/rtl_sim/bin/memory_file_list
can/tags/complete_1/sim/rtl_sim/bin/rtl_file_list
can/tags/complete_1/sim/rtl_sim/bin/sim_file_list
can/tags/complete_1/sim/rtl_sim/log/
can/tags/complete_1/sim/rtl_sim/log/dir_keeper
can/tags/complete_1/sim/rtl_sim/out/
can/tags/complete_1/sim/rtl_sim/out/dir_keeper
can/tags/complete_1/sim/rtl_sim/run/
can/tags/complete_1/sim/rtl_sim/run/clean
can/tags/complete_1/sim/rtl_sim/run/run_sim.scr
can/tags/complete_1/sim/rtl_sim/run/wave.do
can/tags/complete_1/syn/
can/tags/complete_1/syn/libero/
can/tags/complete_1/syn/libero/pinedit.gcf
can/tags/complete_1/syn/synplicity/
can/tags/complete_1/syn/synplicity/can.prj
can/tags/complete_1/syn/synplicity/rev_1/
can/tags/complete_1/syn/synplicity/rev_1/dir_keeper
can/tags/initial/
can/tags/initial/bench/
can/tags/initial/bench/verilog/
can/tags/initial/bench/verilog/can_testbench.v
can/tags/initial/bench/verilog/timescale.v
can/tags/initial/rtl/
can/tags/initial/rtl/verilog/
can/tags/initial/rtl/verilog/can_bitstuff.v
can/tags/initial/rtl/verilog/can_bsp.v
can/tags/initial/rtl/verilog/can_btl.v
can/tags/initial/rtl/verilog/can_defines.v
can/tags/initial/rtl/verilog/can_register.v
can/tags/initial/rtl/verilog/can_register_asyn.v
can/tags/initial/rtl/verilog/can_register_asyn_syn.v
can/tags/initial/rtl/verilog/can_register_syn.v
can/tags/initial/rtl/verilog/can_registers.v
can/tags/initial/rtl/verilog/can_top.v
can/tags/initial/sim/
can/tags/initial/sim/rtl_sim/
can/tags/initial/sim/rtl_sim/bin/
can/tags/initial/sim/rtl_sim/bin/cds.lib
can/tags/initial/sim/rtl_sim/bin/hdl.var
can/tags/initial/sim/rtl_sim/bin/rtl_file_list
can/tags/initial/sim/rtl_sim/bin/sim_file_list
can/tags/initial/sim/rtl_sim/log/
can/tags/initial/sim/rtl_sim/log/dir_keeper
can/tags/initial/sim/rtl_sim/out/
can/tags/initial/sim/rtl_sim/out/dir_keeper
can/tags/initial/sim/rtl_sim/run/
can/tags/initial/sim/rtl_sim/run/clean
can/tags/initial/sim/rtl_sim/run/run_sim.scr
can/tags/initial/sim/rtl_sim/run/wave.do
can/tags/rel_1/
can/tags/rel_1/bench/
can/tags/rel_1/bench/verilog/
can/tags/rel_1/bench/verilog/can_testbench.v
can/tags/rel_1/bench/verilog/can_testbench_defines.v
can/tags/rel_1/bench/verilog/timescale.v
can/tags/rel_1/rtl/
can/tags/rel_1/rtl/verilog/

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