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文件名称:texample1

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    2015-10-24
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    893.88kb
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32-bit shifter, 32-bit.Very goog as a study file.-32-bit shifter, shifter, 32-bit.Very goog as a study file.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

texample1/db/logic_util_heursitic.dat
texample1/db/prev_cmp_shift.qmsg
texample1/db/shift.(0).cnf.cdb
texample1/db/shift.(0).cnf.hdb
texample1/db/shift.amm.cdb
texample1/db/shift.asm.qmsg
texample1/db/shift.asm.rdb
texample1/db/shift.asm_labs.ddb
texample1/db/shift.cbx.xml
texample1/db/shift.cmp.cdb
texample1/db/shift.cmp.hdb
texample1/db/shift.cmp.kpt
texample1/db/shift.cmp.logdb
texample1/db/shift.cmp.rdb
texample1/db/shift.cmp0.ddb
texample1/db/shift.db_info
texample1/db/shift.eda.qmsg
texample1/db/shift.fit.qmsg
texample1/db/shift.hier_info
texample1/db/shift.hif
texample1/db/shift.idb.cdb
texample1/db/shift.lpc.html
texample1/db/shift.lpc.rdb
texample1/db/shift.lpc.txt
texample1/db/shift.map.cdb
texample1/db/shift.map.hdb
texample1/db/shift.map.logdb
texample1/db/shift.map.qmsg
texample1/db/shift.pre_map.cdb
texample1/db/shift.pre_map.hdb
texample1/db/shift.rtlv.hdb
texample1/db/shift.rtlv_sg.cdb
texample1/db/shift.rtlv_sg_swap.cdb
texample1/db/shift.sgdiff.cdb
texample1/db/shift.sgdiff.hdb
texample1/db/shift.sld_design_entry.sci
texample1/db/shift.sld_design_entry_dsc.sci
texample1/db/shift.smart_action.txt
texample1/db/shift.sta.qmsg
texample1/db/shift.sta.rdb
texample1/db/shift.sta_cmp.5_slow.tdb
texample1/db/shift.syn_hier_info
texample1/db/shift.tis_db_list.ddb
texample1/db/shift.tmw_info
texample1/incremental_db/compiled_partitions/shift.db_info
texample1/incremental_db/compiled_partitions/shift.root_partition.map.kpt
texample1/incremental_db/README
texample1/shift.asm.rpt
texample1/shift.done
texample1/shift.eda.rpt
texample1/shift.fit.rpt
texample1/shift.fit.smsg
texample1/shift.fit.summary
texample1/shift.flow.rpt
texample1/shift.map.rpt
texample1/shift.map.summary
texample1/shift.pin
texample1/shift.pof
texample1/shift.qpf
texample1/shift.qsf
texample1/shift.sta.rpt
texample1/shift.sta.summary
texample1/shift.v
texample1/shift.v.bak
texample1/shift_nativelink_simulation.rpt
texample1/simulation/modelsim/modelsim.ini
texample1/simulation/modelsim/msim_transcript
texample1/simulation/modelsim/rtl_work/shift/verilog.prw
texample1/simulation/modelsim/rtl_work/shift/verilog.psm
texample1/simulation/modelsim/rtl_work/shift/_primary.dat
texample1/simulation/modelsim/rtl_work/shift/_primary.dbs
texample1/simulation/modelsim/rtl_work/shift/_primary.vhd
texample1/simulation/modelsim/rtl_work/shift_vlg_tst/verilog.prw
texample1/simulation/modelsim/rtl_work/shift_vlg_tst/verilog.psm
texample1/simulation/modelsim/rtl_work/shift_vlg_tst/_primary.dat
texample1/simulation/modelsim/rtl_work/shift_vlg_tst/_primary.dbs
texample1/simulation/modelsim/rtl_work/shift_vlg_tst/_primary.vhd
texample1/simulation/modelsim/rtl_work/_info
texample1/simulation/modelsim/rtl_work/_vmake
texample1/simulation/modelsim/shift.sft
texample1/simulation/modelsim/shift.vo
texample1/simulation/modelsim/shift.vt
texample1/simulation/modelsim/shift.vt.bak
texample1/simulation/modelsim/shift_modelsim.xrf
texample1/simulation/modelsim/shift_run_msim_rtl_verilog.do
texample1/simulation/modelsim/shift_run_msim_rtl_verilog.do.bak
texample1/simulation/modelsim/shift_run_msim_rtl_verilog.do.bak1
texample1/simulation/modelsim/shift_v.sdo
texample1/simulation/modelsim/vsim.wlf
texample1/simulation/modelsim/rtl_work/shift
texample1/simulation/modelsim/rtl_work/shift_vlg_tst
texample1/simulation/modelsim/rtl_work/_temp
texample1/simulation/modelsim/rtl_work
texample1/incremental_db/compiled_partitions
texample1/simulation/modelsim
texample1/db
texample1/incremental_db
texample1/simulation
texample1

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