文件名称:XOR_tree
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- 上传时间:2015-11-10
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文件大小:4.12mb
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This source code is a check node unit for LDPC decoder.
The language is Verilog HDL.
The language is Verilog HDL.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
bench/verilog/tb_bit_serial.v
bench/verilog/tb_bit_serial.v.bak
bench/verilog/tb_bit_serial_withXOR.v
bench/verilog/tb_bit_serial_withXOR.v.bak
bench/verilog/tb_FAID_sub_MF.v
bench/verilog/tb_FAID_sub_MF.v.bak
bench/verilog/tb_mVG_8.v
bench/verilog/tb_mVG_8.v.bak
bench/verilog/tb_new2_cont.v
bench/verilog/tb_new2_cont.v.bak
bench/verilog/tb_new2_top_test_pro_min.v
bench/verilog/tb_new2_top_test_pro_min.v.bak
bench/verilog/tb_new_top_test_pro_min.v
bench/verilog/tb_temp.v
bench/verilog/tb_temp.v.bak
bench/verilog/tb_temp2.v
bench/verilog/tb_temp2.v.bak
design/verilog/Bit-serial.v
design/verilog/bit_serial.v
design/verilog/bit_serial.v.bak
design/verilog/bit_serial_finder.v
design/verilog/bit_serial_finder.v.bak
design/verilog/bit_serial_withXOR.v
design/verilog/bit_serial_withXOR.v.bak
design/verilog/CU.v
design/verilog/CU.v.bak
design/verilog/FAID_sub_MF.v
design/verilog/FAID_sub_MF.v.bak
design/verilog/mVG_16.v
design/verilog/mVG_16.v.bak
design/verilog/mVG_2.v
design/verilog/mVG_2.v.bak
design/verilog/mVG_32.v
design/verilog/mVG_32.v.bak
design/verilog/mVG_4.v
design/verilog/mVG_4.v.bak
design/verilog/mVG_64.v
design/verilog/mVG_64.v.bak
design/verilog/mVG_8.v
design/verilog/mVG_8.v.bak
design/verilog/mVU.v
design/verilog/mVU.v.bak
design/verilog/new2_cont.v
design/verilog/new2_cont.v.bak
design/verilog/new2_top_test_pro_min.v
design/verilog/new2_top_test_pro_min.v.bak
design/verilog/new_flag_module.v
design/verilog/new_flag_module.v.bak
design/verilog/new_sel_gen.v
design/verilog/new_sel_gen.v.bak
design/verilog/new_top_flag.v
design/verilog/new_top_flag.v.bak
design/verilog/new_top_test_pro_min.v
design/verilog/new_top_test_pro_min.v.bak
design/verilog/priencr.v
design/verilog/priencr.v.bak
design/verilog/recursive_test.v
design/verilog/temp.v
design/verilog/temp.v.bak
design/verilog/temp2.v
design/verilog/temp2.v.bak
design/verilog/UZD.v
design/verilog/UZD.v.bak
design/verilog/XOR_tree.v
design/verilog/XOR_tree.v.bak
ise/AutoConstraint_bit_serial.sdc
ise/AutoConstraint_bit_serial_finder.sdc
ise/AutoConstraint_bit_serial_withXOR.sdc
ise/AutoConstraint_FAID_sub_MF.sdc
ise/AutoConstraint_mVG_16.sdc
ise/AutoConstraint_mVG_32.sdc
ise/AutoConstraint_mVG_4.sdc
ise/AutoConstraint_mVG_64.sdc
ise/AutoConstraint_new2_cont.sdc
ise/AutoConstraint_new2_top_test_pro_min.sdc
ise/AutoConstraint_new_top_test_pro_min.sdc
ise/AutoConstraint_temp.sdc
ise/AutoConstraint_temp2.sdc
ise/AutoConstraint_UZD.sdc
ise/AutoConstraint_XOR_tree.sdc
ise/backup/bit_serial.srr
ise/backup/bit_serial_finder.srr
ise/backup/bit_serial_withXOR.srr
ise/backup/FAID_sub_MF.srr
ise/backup/mVG_2k.srr
ise/backup/mVG_4.srr
ise/backup/mVG_64.srr
ise/backup/new2_cont.srr
ise/backup/new2_top_test_pro_min.srr
ise/backup/new_top_test_pro_min.srr
ise/backup/temp.srr
ise/backup/temp2.srr
ise/backup/UZD.srr
ise/backup/XOR_tree.srr
ise/bit_serial.fse
ise/bit_serial.htm
ise/bit_serial.map
ise/bit_serial.sap
ise/bit_serial.sdc
ise/bit_serial.szr
ise/bit_serial.tah
ise/bit_serial_finder.bld
ise/bit_serial_finder.cmd_log
ise/bit_serial_finder.fse
ise/bit_serial_finder.htm
ise/bit_serial_finder.log
ise/bit_serial_finder.map
ise/bit_serial_finder.ncd
ise/bit_serial_finder.ngd
ise/bit_serial_finder.pad
ise/bit_serial_finder.par
ise/bit_serial_finder.pcf
ise/bit_serial_finder.sap
ise/bit_serial_finder.sdc
ise/bit_serial_finder.szr
ise/bit_serial_finder.tah
ise/bit_serial_finder.twr
ise/bit_serial_finder.twx
ise/bit_serial_finder.unroutes
ise/bit_serial_finder.xpi
ise/bit_serial_finder_guide.ncd
ise/bit_serial_finder_map.map
ise/bit_serial_finder_map.mrp
ise/bit_serial_finder_map.ncd
ise/bit_serial_finder_map.ngm
ise/bit_serial_finder_pad.csv
ise/bit_serial_finder_pad.txt
ise/bit_serial_finder_summary.html
ise/bit_serial_finder_summary.xml
ise/bit_serial_finder_usage.xml
ise/bit_serial_summary.html
ise/bit_serial_withXOR.fse
ise/bit_serial_withXOR.htm
ise/bit_serial_withXOR.map
ise/bit_serial_withXOR.sap
ise/bit_serial_withXOR.sdc
ise/bit_serial_withXOR.spl
ise/bit_serial_withXOR.sym
ise/bit_serial_withXOR.szr
ise/bit_serial_withXOR.tah
ise/bit_serial_withXOR_summary.html
ise/coreip/
ise/FAID_sub_MF.bld
ise/FAID_sub_MF.cmd_log
ise/FAID_sub_MF.fse
ise/FAID_sub_MF.htm
ise/FAID_sub_MF.log
ise/FAID_sub_MF.map
ise/FAID_sub_MF.ncd
ise/FAID_sub_MF.ngd
ise/FAID_sub_MF.pad
ise/FAID_sub_MF.par
ise/FAID_sub_MF.pcf
ise/FAID_sub_MF.sap
ise/FAID_sub_MF.sdc
ise/FAID_sub_MF.szr
ise/FAID_sub_MF.tah
ise/faid_sub_mf.twr
ise/faid_sub_mf.twx
ise/FAID_sub_MF.unroutes
ise/FAID_sub_MF.xpi
ise/FAID_sub_MF_guide.ncd
ise/FAID_sub_MF_map.map
ise/FAID_sub_MF_map.mrp
ise/FAID_sub_MF_map.ncd
ise/FAID_sub_MF_map.ngm
ise/FAID_sub_MF_pad.csv
ise/FAID_sub_MF_pad.txt
ise/FAID_sub_MF_summary.html
ise/FAID_sub_MF_summary.xml
ise/FAID_sub_MF_usage.xml
ise/ise.ise
ise/ise.ise_ISE_Backup
ise/ise.restore
ise/islands.tcl
ise/mVG_16.fse
ise/mVG_16.htm
ise/mVG_16.map
ise/mVG_16.sap
ise/mVG_16.sdc
ise/mVG_16.szr
ise/mVG_16_summary.html
ise/mVG_2k.htm
ise/mVG_2k.ise_created
ise/mVG_2k.prj
ise/mVG_2k.sdc
ise/mVG_2k.srr
ise/mVG_2k.srs
ise/mVG_2k.tlg
ise/mVG_2k_compile.tcl
ise/mVG_2k_map.tcl
ise/mVG_2k_summary.html
ise/mVG_2_summary.
bench/verilog/tb_bit_serial.v.bak
bench/verilog/tb_bit_serial_withXOR.v
bench/verilog/tb_bit_serial_withXOR.v.bak
bench/verilog/tb_FAID_sub_MF.v
bench/verilog/tb_FAID_sub_MF.v.bak
bench/verilog/tb_mVG_8.v
bench/verilog/tb_mVG_8.v.bak
bench/verilog/tb_new2_cont.v
bench/verilog/tb_new2_cont.v.bak
bench/verilog/tb_new2_top_test_pro_min.v
bench/verilog/tb_new2_top_test_pro_min.v.bak
bench/verilog/tb_new_top_test_pro_min.v
bench/verilog/tb_temp.v
bench/verilog/tb_temp.v.bak
bench/verilog/tb_temp2.v
bench/verilog/tb_temp2.v.bak
design/verilog/Bit-serial.v
design/verilog/bit_serial.v
design/verilog/bit_serial.v.bak
design/verilog/bit_serial_finder.v
design/verilog/bit_serial_finder.v.bak
design/verilog/bit_serial_withXOR.v
design/verilog/bit_serial_withXOR.v.bak
design/verilog/CU.v
design/verilog/CU.v.bak
design/verilog/FAID_sub_MF.v
design/verilog/FAID_sub_MF.v.bak
design/verilog/mVG_16.v
design/verilog/mVG_16.v.bak
design/verilog/mVG_2.v
design/verilog/mVG_2.v.bak
design/verilog/mVG_32.v
design/verilog/mVG_32.v.bak
design/verilog/mVG_4.v
design/verilog/mVG_4.v.bak
design/verilog/mVG_64.v
design/verilog/mVG_64.v.bak
design/verilog/mVG_8.v
design/verilog/mVG_8.v.bak
design/verilog/mVU.v
design/verilog/mVU.v.bak
design/verilog/new2_cont.v
design/verilog/new2_cont.v.bak
design/verilog/new2_top_test_pro_min.v
design/verilog/new2_top_test_pro_min.v.bak
design/verilog/new_flag_module.v
design/verilog/new_flag_module.v.bak
design/verilog/new_sel_gen.v
design/verilog/new_sel_gen.v.bak
design/verilog/new_top_flag.v
design/verilog/new_top_flag.v.bak
design/verilog/new_top_test_pro_min.v
design/verilog/new_top_test_pro_min.v.bak
design/verilog/priencr.v
design/verilog/priencr.v.bak
design/verilog/recursive_test.v
design/verilog/temp.v
design/verilog/temp.v.bak
design/verilog/temp2.v
design/verilog/temp2.v.bak
design/verilog/UZD.v
design/verilog/UZD.v.bak
design/verilog/XOR_tree.v
design/verilog/XOR_tree.v.bak
ise/AutoConstraint_bit_serial.sdc
ise/AutoConstraint_bit_serial_finder.sdc
ise/AutoConstraint_bit_serial_withXOR.sdc
ise/AutoConstraint_FAID_sub_MF.sdc
ise/AutoConstraint_mVG_16.sdc
ise/AutoConstraint_mVG_32.sdc
ise/AutoConstraint_mVG_4.sdc
ise/AutoConstraint_mVG_64.sdc
ise/AutoConstraint_new2_cont.sdc
ise/AutoConstraint_new2_top_test_pro_min.sdc
ise/AutoConstraint_new_top_test_pro_min.sdc
ise/AutoConstraint_temp.sdc
ise/AutoConstraint_temp2.sdc
ise/AutoConstraint_UZD.sdc
ise/AutoConstraint_XOR_tree.sdc
ise/backup/bit_serial.srr
ise/backup/bit_serial_finder.srr
ise/backup/bit_serial_withXOR.srr
ise/backup/FAID_sub_MF.srr
ise/backup/mVG_2k.srr
ise/backup/mVG_4.srr
ise/backup/mVG_64.srr
ise/backup/new2_cont.srr
ise/backup/new2_top_test_pro_min.srr
ise/backup/new_top_test_pro_min.srr
ise/backup/temp.srr
ise/backup/temp2.srr
ise/backup/UZD.srr
ise/backup/XOR_tree.srr
ise/bit_serial.fse
ise/bit_serial.htm
ise/bit_serial.map
ise/bit_serial.sap
ise/bit_serial.sdc
ise/bit_serial.szr
ise/bit_serial.tah
ise/bit_serial_finder.bld
ise/bit_serial_finder.cmd_log
ise/bit_serial_finder.fse
ise/bit_serial_finder.htm
ise/bit_serial_finder.log
ise/bit_serial_finder.map
ise/bit_serial_finder.ncd
ise/bit_serial_finder.ngd
ise/bit_serial_finder.pad
ise/bit_serial_finder.par
ise/bit_serial_finder.pcf
ise/bit_serial_finder.sap
ise/bit_serial_finder.sdc
ise/bit_serial_finder.szr
ise/bit_serial_finder.tah
ise/bit_serial_finder.twr
ise/bit_serial_finder.twx
ise/bit_serial_finder.unroutes
ise/bit_serial_finder.xpi
ise/bit_serial_finder_guide.ncd
ise/bit_serial_finder_map.map
ise/bit_serial_finder_map.mrp
ise/bit_serial_finder_map.ncd
ise/bit_serial_finder_map.ngm
ise/bit_serial_finder_pad.csv
ise/bit_serial_finder_pad.txt
ise/bit_serial_finder_summary.html
ise/bit_serial_finder_summary.xml
ise/bit_serial_finder_usage.xml
ise/bit_serial_summary.html
ise/bit_serial_withXOR.fse
ise/bit_serial_withXOR.htm
ise/bit_serial_withXOR.map
ise/bit_serial_withXOR.sap
ise/bit_serial_withXOR.sdc
ise/bit_serial_withXOR.spl
ise/bit_serial_withXOR.sym
ise/bit_serial_withXOR.szr
ise/bit_serial_withXOR.tah
ise/bit_serial_withXOR_summary.html
ise/coreip/
ise/FAID_sub_MF.bld
ise/FAID_sub_MF.cmd_log
ise/FAID_sub_MF.fse
ise/FAID_sub_MF.htm
ise/FAID_sub_MF.log
ise/FAID_sub_MF.map
ise/FAID_sub_MF.ncd
ise/FAID_sub_MF.ngd
ise/FAID_sub_MF.pad
ise/FAID_sub_MF.par
ise/FAID_sub_MF.pcf
ise/FAID_sub_MF.sap
ise/FAID_sub_MF.sdc
ise/FAID_sub_MF.szr
ise/FAID_sub_MF.tah
ise/faid_sub_mf.twr
ise/faid_sub_mf.twx
ise/FAID_sub_MF.unroutes
ise/FAID_sub_MF.xpi
ise/FAID_sub_MF_guide.ncd
ise/FAID_sub_MF_map.map
ise/FAID_sub_MF_map.mrp
ise/FAID_sub_MF_map.ncd
ise/FAID_sub_MF_map.ngm
ise/FAID_sub_MF_pad.csv
ise/FAID_sub_MF_pad.txt
ise/FAID_sub_MF_summary.html
ise/FAID_sub_MF_summary.xml
ise/FAID_sub_MF_usage.xml
ise/ise.ise
ise/ise.ise_ISE_Backup
ise/ise.restore
ise/islands.tcl
ise/mVG_16.fse
ise/mVG_16.htm
ise/mVG_16.map
ise/mVG_16.sap
ise/mVG_16.sdc
ise/mVG_16.szr
ise/mVG_16_summary.html
ise/mVG_2k.htm
ise/mVG_2k.ise_created
ise/mVG_2k.prj
ise/mVG_2k.sdc
ise/mVG_2k.srr
ise/mVG_2k.srs
ise/mVG_2k.tlg
ise/mVG_2k_compile.tcl
ise/mVG_2k_map.tcl
ise/mVG_2k_summary.html
ise/mVG_2_summary.
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