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文件名称:asyn_fifo2

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采用Verilog语言,使用FPGA内部IP核FIFO模块,实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
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asyn_fifo2/asyn_fifo2.qsf
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asyn_fifo2/db/
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