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文件名称:xilinx_PCIeLogiCore

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2015-11-17
  • 文件大小：
    4.31mb
  • 已下载：
    0次
  • 提 供 者：
    hel***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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基于xilinx fpga的PCIE逻辑IP核-thisis a xilinx_PCIeLogiCore
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/components.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/downstreamSim.gise
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/downstreamSim.wcfg
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/downstreamSim.xise
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/mockApplication.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/string_utilities_sim_pkg.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/string_utilities_synth_pkg.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/testbench_top.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/time_utilities_pkg.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_drp_chanalign_fix_3752_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_rx_valid_filter_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_tx_sync_rate_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_wrapper_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_rport_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_v6_rp.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_brams_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_top_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_clocking_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_gtx_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_lane_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_misc_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_reset_delay_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_upconfig_fix_3451_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_cfg.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_pl.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_rx.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_tx.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/tests.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/test_interface.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/xilinx_pcie_2_0_rport_v6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/s6_pcie_readme.txt
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/doc/s6_pcie_ds718.pdf
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/doc/s6_pcie_ug654.pdf
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/pcie_app_s6.v
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/pcie_app_s6.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO.v
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO_32_RX_ENGINE.v
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO_32_RX_ENGINE.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO_32_TX_ENGINE.v
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO_32_TX_ENGINE.vhd
Designing a LogiCORE PCI Express System/labs/downstreamSim/SP605/VHDL/S6PCIeEP/example_design/PIO_EP.v
Designing a LogiCORE PCI Express S

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