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文件名称:VHDL-projects

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-11-18
  • 文件大小：
    1.44mb
  • 已下载：
    0次
  • 提 供 者：
    Jaro****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VHDL projects/project4/.lso
VHDL projects/project4/citac.cmd_log
VHDL projects/project4/citac.spl
VHDL projects/project4/citac.sym
VHDL projects/project4/citac.vhd
VHDL projects/project4/Dekoder.cmd_log
VHDL projects/project4/Dekoder.spl
VHDL projects/project4/Dekoder.sym
VHDL projects/project4/Dekoder.vhd
VHDL projects/project4/Dekoder_summary.html
VHDL projects/project4/delicka.cmd_log
VHDL projects/project4/delicka.prj
VHDL projects/project4/delicka.spl
VHDL projects/project4/delicka.stx
VHDL projects/project4/delicka.sym
VHDL projects/project4/delicka.vhd
VHDL projects/project4/delicka.xst
VHDL projects/project4/delicka_vhdl.prj
VHDL projects/project4/iseconfig/Dekoder.xreport
VHDL projects/project4/iseconfig/projekt4_kizek.projectmgr
VHDL projects/project4/iseconfig/TOPsheet.xreport
VHDL projects/project4/pa.fromNetlist.tcl
VHDL projects/project4/pepExtractor.prj
VHDL projects/project4/planAhead.ngc2edif.log
VHDL projects/project4/planAhead_run_1/planAhead.jou
VHDL projects/project4/planAhead_run_1/planAhead.log
VHDL projects/project4/planAhead_run_1/planAhead_run.log
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/constrs_1/designprops.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/constrs_1/fileset.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/constrs_1/usercols.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/runs/impl_1.psg
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/runs/runs.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/sources_1/chipscope.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/sources_1/fileset.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/sources_1/ports.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.data/wt/webtalk_pa.xml
VHDL projects/project4/planAhead_run_1/projekt4_kizek.ppr
VHDL projects/project4/projekt4_kizek.gise
VHDL projects/project4/projekt4_kizek.xise
VHDL projects/project4/sch2HdlBatchFile
VHDL projects/project4/topsheet.bgn
VHDL projects/project4/topsheet.bit
VHDL projects/project4/TOPsheet.bld
VHDL projects/project4/TOPsheet.cmd_log
VHDL projects/project4/topsheet.drc
VHDL projects/project4/TOPsheet.jhd
VHDL projects/project4/TOPsheet.lso
VHDL projects/project4/TOPsheet.ncd
VHDL projects/project4/TOPsheet.ngc
VHDL projects/project4/TOPsheet.ngd
VHDL projects/project4/TOPsheet.ngr
VHDL projects/project4/TOPsheet.pad
VHDL projects/project4/TOPsheet.par
VHDL projects/project4/TOPsheet.pcf
VHDL projects/project4/TOPsheet.prj
VHDL projects/project4/TOPsheet.ptwx
VHDL projects/project4/TOPsheet.sch
VHDL projects/project4/TOPsheet.stx
VHDL projects/project4/TOPsheet.syr
VHDL projects/project4/TOPsheet.twr
VHDL projects/project4/TOPsheet.twx
VHDL projects/project4/TOPsheet.ucf
VHDL projects/project4/TOPsheet.unroutes
VHDL projects/project4/TOPsheet.ut
VHDL projects/project4/TOPsheet.vhf
VHDL projects/project4/TOPsheet.xpi
VHDL projects/project4/TOPsheet.xst
VHDL projects/project4/TOPsheet_bitgen.xwbt
VHDL projects/project4/TOPsheet_envsettings.html
VHDL projects/project4/TOPsheet_guide.ncd
VHDL projects/project4/TOPsheet_map.map
VHDL projects/project4/TOPsheet_map.mrp
VHDL projects/project4/TOPsheet_map.ncd
VHDL projects/project4/TOPsheet_map.ngm
VHDL projects/project4/TOPsheet_map.xrpt
VHDL projects/project4/TOPsheet_ngdbuild.xrpt
VHDL projects/project4/TOPsheet_pad.csv
VHDL projects/project4/TOPsheet_pad.txt
VHDL projects/project4/TOPsheet_par.xrpt
VHDL projects/project4/TOPsheet_summary.html
VHDL projects/project4/TOPsheet_summary.xml
VHDL projects/project4/TOPsheet_usage.xml
VHDL projects/project4/TOPsheet_vhdl.prj
VHDL projects/project4/TOPsheet_xst.xrpt
VHDL projects/project4/webtalk.log
VHDL projects/project4/webtalk_pn.xml
VHDL projects/project4/xlnx_auto_0_xdb/cst.xbcd
VHDL projects/project4/xst/work/hdllib.ref
VHDL projects/project4/xst/work/hdpdeps.ref
VHDL projects/project4/xst/work/sub00/vhpl00.vho
VHDL projects/project4/xst/work/sub00/vhpl01.vho
VHDL projects/project4/xst/work/sub00/vhpl02.vho
VHDL projects/project4/xst/work/sub00/vhpl03.vho
VHDL projects/project4/xst/work/sub00/vhpl04.vho
VHDL projects/project4/xst/work/sub00/vhpl05.vho
VHDL projects/project4/xst/work/sub00/vhpl06.vho
VHDL projects/project4/xst/work/sub00/vhpl07.vho
VHDL projects/project4/xst/work/sub00/vhpl08.vho
VHDL projects/project4/xst/work/sub00/vhpl09.vho
VHDL projects/project4/_ngo/netlist.lst
VHDL projects/project4/_xmsgs/bitgen.xmsgs
VHDL projects/project4/_xmsgs/map.xmsgs
VHDL projects/project4/_xmsgs/ngdbuild.xmsgs
VHDL projects/project4/_xmsgs/par.xmsgs
VHDL projects/project4/_xmsgs/pn_parser.xmsgs
VHDL projects/project4/_xmsgs/trce.xmsgs
VHDL projects/project4/_xmsgs/xst.xmsgs
VHDL projects/project5/Dekoder.sym
VHDL projects/project5/Dekoder.vhd
VHDL projects/project5/delicka.sym
VHDL projects/project5/delicka.vhd
VHDL projects/project5/iseconfig/projekt5_kizek_v3.projectmgr
VHDL projects/project5/iseconfig/TOPsheet.xreport
VHDL projects/project5/pa.fromNetlist.tcl
VHDL projects/project5/planAhead.ngc2edif.log
VHDL projects/project5/planAhead_run_1/planAhead.jou
VHDL pr

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